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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_0_in_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_0_in_endofpacket : IN STD_LOGIC;
                 signal clock_0_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_0_in_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_0_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_0_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_in_read : OUT STD_LOGIC;
                 signal clock_0_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_0_in_reset_n : OUT STD_LOGIC;
                 signal clock_0_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_0_in_write : OUT STD_LOGIC;
                 signal clock_0_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_0_data_master_granted_clock_0_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_0_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_0_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_0_in : OUT STD_LOGIC;
                 signal d1_clock_0_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_0_in_arbitrator : entity is FALSE;
end entity clock_0_in_arbitrator;


architecture europa of clock_0_in_arbitrator is
                signal clock_0_in_allgrants :  STD_LOGIC;
                signal clock_0_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_0_in_any_bursting_master_saved_grant :  STD_LOGIC;
                signal clock_0_in_any_continuerequest :  STD_LOGIC;
                signal clock_0_in_arb_counter_enable :  STD_LOGIC;
                signal clock_0_in_arb_share_counter :  STD_LOGIC;
                signal clock_0_in_arb_share_counter_next_value :  STD_LOGIC;
                signal clock_0_in_arb_share_set_values :  STD_LOGIC;
                signal clock_0_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_0_in_begins_xfer :  STD_LOGIC;
                signal clock_0_in_end_xfer :  STD_LOGIC;
                signal clock_0_in_firsttransfer :  STD_LOGIC;
                signal clock_0_in_grant_vector :  STD_LOGIC;
                signal clock_0_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_0_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_0_in_master_qreq_vector :  STD_LOGIC;
                signal clock_0_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_0_in_pretend_byte_enable :  STD_LOGIC;
                signal clock_0_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_0_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_0_in_waits_for_read :  STD_LOGIC;
                signal clock_0_in_waits_for_write :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_clock_0_in :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_clock_0_in :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_0_in_waitrequest_from_sa :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_clock_0_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_clock_0_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_clock_0_in :  STD_LOGIC;
                signal shifted_address_to_clock_0_in_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_clock_0_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_0_in_end_xfer;
      end if;
    end if;

  end process;

  clock_0_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_clock_0_in);
  --assign clock_0_in_readdata_from_sa = clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_0_in_readdata_from_sa <= clock_0_in_readdata;
  internal_cpu_0_data_master_requests_clock_0_in <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000100000010000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --assign clock_0_in_waitrequest_from_sa = clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_0_in_waitrequest_from_sa <= clock_0_in_waitrequest;
  --clock_0_in_arb_share_counter set values, which is an e_mux
  clock_0_in_arb_share_set_values <= std_logic'('1');
  --clock_0_in_non_bursting_master_requests mux, which is an e_mux
  clock_0_in_non_bursting_master_requests <= internal_cpu_0_data_master_requests_clock_0_in;
  --clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
  clock_0_in_any_bursting_master_saved_grant <= std_logic'('0');
  --clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_0_in_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(clock_0_in_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_0_in_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(clock_0_in_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_0_in_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --clock_0_in_allgrants all slave grants, which is an e_mux
  clock_0_in_allgrants <= clock_0_in_grant_vector;
  --clock_0_in_end_xfer assignment, which is an e_assign
  clock_0_in_end_xfer <= NOT ((clock_0_in_waits_for_read OR clock_0_in_waits_for_write));
  --end_xfer_arb_share_counter_term_clock_0_in arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_clock_0_in <= clock_0_in_end_xfer AND (((NOT clock_0_in_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_0_in_arb_counter_enable <= ((end_xfer_arb_share_counter_term_clock_0_in AND clock_0_in_allgrants)) OR ((end_xfer_arb_share_counter_term_clock_0_in AND NOT clock_0_in_non_bursting_master_requests));
  --clock_0_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_0_in_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clock_0_in_arb_counter_enable) = '1' then 
        clock_0_in_arb_share_counter <= clock_0_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_0_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_0_in_master_qreq_vector AND end_xfer_arb_share_counter_term_clock_0_in)) OR ((end_xfer_arb_share_counter_term_clock_0_in AND NOT clock_0_in_non_bursting_master_requests)))) = '1' then 
        clock_0_in_slavearbiterlockenable <= clock_0_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master clock_0/in arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= clock_0_in_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_0_in_slavearbiterlockenable2 <= clock_0_in_arb_share_counter_next_value;
  --cpu_0/data_master clock_0/in arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= clock_0_in_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_0_in_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_clock_0_in <= internal_cpu_0_data_master_requests_clock_0_in AND NOT ((((cpu_0_data_master_read AND (NOT cpu_0_data_master_waitrequest))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))));
  --clock_0_in_writedata mux, which is an e_mux
  clock_0_in_writedata <= cpu_0_data_master_writedata (7 DOWNTO 0);
  --assign clock_0_in_endofpacket_from_sa = clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_0_in_endofpacket_from_sa <= clock_0_in_endofpacket;
  --master is always granted when requested
  internal_cpu_0_data_master_granted_clock_0_in <= internal_cpu_0_data_master_qualified_request_clock_0_in;
  --cpu_0/data_master saved-grant clock_0/in, which is an e_assign
  cpu_0_data_master_saved_grant_clock_0_in <= internal_cpu_0_data_master_requests_clock_0_in;
  --allow new arb cycle for clock_0/in, which is an e_assign
  clock_0_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_0_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_0_in_master_qreq_vector <= std_logic'('1');
  --clock_0_in_reset_n assignment, which is an e_assign
  clock_0_in_reset_n <= reset_n;
  --clock_0_in_firsttransfer first transaction, which is an e_assign
  clock_0_in_firsttransfer <= NOT ((clock_0_in_slavearbiterlockenable AND clock_0_in_any_continuerequest));
  --clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_0_in_beginbursttransfer_internal <= clock_0_in_begins_xfer;
  --clock_0_in_read assignment, which is an e_mux
  clock_0_in_read <= internal_cpu_0_data_master_granted_clock_0_in AND cpu_0_data_master_read;
  --clock_0_in_write assignment, which is an e_mux
  clock_0_in_write <= ((internal_cpu_0_data_master_granted_clock_0_in AND cpu_0_data_master_write)) AND clock_0_in_pretend_byte_enable;
  shifted_address_to_clock_0_in_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --clock_0_in_address mux, which is an e_mux
  clock_0_in_address <= A_EXT (A_SRL(shifted_address_to_clock_0_in_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --slaveid clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_0_in_nativeaddress <= A_EXT (A_SRL(cpu_0_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_clock_0_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_0_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_0_in_end_xfer <= clock_0_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_0_in_waits_for_read in a cycle, which is an e_mux
  clock_0_in_waits_for_read <= clock_0_in_in_a_read_cycle AND internal_clock_0_in_waitrequest_from_sa;
  --clock_0_in_in_a_read_cycle assignment, which is an e_assign
  clock_0_in_in_a_read_cycle <= internal_cpu_0_data_master_granted_clock_0_in AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_0_in_in_a_read_cycle;
  --clock_0_in_waits_for_write in a cycle, which is an e_mux
  clock_0_in_waits_for_write <= clock_0_in_in_a_write_cycle AND internal_clock_0_in_waitrequest_from_sa;
  --clock_0_in_in_a_write_cycle assignment, which is an e_assign
  clock_0_in_in_a_write_cycle <= internal_cpu_0_data_master_granted_clock_0_in AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_0_in_in_a_write_cycle;
  wait_for_clock_0_in_counter <= std_logic'('0');
  --clock_0_in_pretend_byte_enable byte enable port mux, which is an e_mux
  clock_0_in_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_clock_0_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  clock_0_in_waitrequest_from_sa <= internal_clock_0_in_waitrequest_from_sa;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_clock_0_in <= internal_cpu_0_data_master_granted_clock_0_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_clock_0_in <= internal_cpu_0_data_master_qualified_request_clock_0_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_clock_0_in <= internal_cpu_0_data_master_requests_clock_0_in;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_0_out_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_0_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_out_granted_rcv_dv_s1 : IN STD_LOGIC;
                 signal clock_0_out_qualified_request_rcv_dv_s1 : IN STD_LOGIC;
                 signal clock_0_out_read : IN STD_LOGIC;
                 signal clock_0_out_read_data_valid_rcv_dv_s1 : IN STD_LOGIC;
                 signal clock_0_out_requests_rcv_dv_s1 : IN STD_LOGIC;
                 signal clock_0_out_write : IN STD_LOGIC;
                 signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal d1_rcv_dv_s1_end_xfer : IN STD_LOGIC;
                 signal rcv_dv_s1_readdata_from_sa : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_0_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_0_out_reset_n : OUT STD_LOGIC;
                 signal clock_0_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_0_out_arbitrator : entity is FALSE;
end entity clock_0_out_arbitrator;


architecture europa of clock_0_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_0_out_address_last_time :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_out_read_last_time :  STD_LOGIC;
                signal clock_0_out_run :  STD_LOGIC;
                signal clock_0_out_write_last_time :  STD_LOGIC;
                signal clock_0_out_writedata_last_time :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal internal_clock_0_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_clock_0_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_0_out_qualified_request_rcv_dv_s1 OR NOT clock_0_out_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_rcv_dv_s1_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_0_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_0_out_qualified_request_rcv_dv_s1 OR NOT clock_0_out_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_0_out_write)))))))));
  --cascaded wait assignment, which is an e_assign
  clock_0_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_0_out_address_to_slave <= clock_0_out_address;
  --clock_0/out readdata mux, which is an e_mux
  clock_0_out_readdata <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(rcv_dv_s1_readdata_from_sa));
  --actual waitrequest port, which is an e_assign
  internal_clock_0_out_waitrequest <= NOT clock_0_out_run;
  --clock_0_out_reset_n assignment, which is an e_assign
  clock_0_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_0_out_address_to_slave <= internal_clock_0_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_0_out_waitrequest <= internal_clock_0_out_waitrequest;
--synthesis translate_off
    --clock_0_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_address_last_time <= std_logic_vector'("00");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_address_last_time <= clock_0_out_address;
        end if;
      end if;

    end process;

    --clock_0/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_0_out_waitrequest AND ((clock_0_out_read OR clock_0_out_write));
        end if;
      end if;

    end process;

    --clock_0_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_address, clock_0_out_address_last_time)
    VARIABLE write_line : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_0_out_address /= clock_0_out_address_last_time))))) = '1' then 
          write(write_line, now);
          write(write_line, string'(": "));
          write(write_line, string'("clock_0_out_address did not heed wait!!!"));
          write(output, write_line.all);
          deallocate (write_line);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_read_last_time <= clock_0_out_read;
        end if;
      end if;

    end process;

    --clock_0_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_read, clock_0_out_read_last_time)
    VARIABLE write_line1 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_0_out_read) /= std_logic'(clock_0_out_read_last_time)))))) = '1' then 
          write(write_line1, now);
          write(write_line1, string'(": "));
          write(write_line1, string'("clock_0_out_read did not heed wait!!!"));
          write(output, write_line1.all);
          deallocate (write_line1);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_write_last_time <= clock_0_out_write;
        end if;
      end if;

    end process;

    --clock_0_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_write, clock_0_out_write_last_time)
    VARIABLE write_line2 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_0_out_write) /= std_logic'(clock_0_out_write_last_time)))))) = '1' then 
          write(write_line2, now);
          write(write_line2, string'(": "));
          write(write_line2, string'("clock_0_out_write did not heed wait!!!"));
          write(output, write_line2.all);
          deallocate (write_line2);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_0_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_0_out_writedata_last_time <= std_logic_vector'("00000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_0_out_writedata_last_time <= clock_0_out_writedata;
        end if;
      end if;

    end process;

    --clock_0_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_0_out_write, clock_0_out_writedata, clock_0_out_writedata_last_time)
    VARIABLE write_line3 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_0_out_writedata /= clock_0_out_writedata_last_time)))) AND clock_0_out_write)) = '1' then 
          write(write_line3, now);
          write(write_line3, string'(": "));
          write(write_line3, string'("clock_0_out_writedata did not heed wait!!!"));
          write(output, write_line3.all);
          deallocate (write_line3);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_1_in_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_1_in_endofpacket : IN STD_LOGIC;
                 signal clock_1_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_1_in_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_1_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_1_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_in_read : OUT STD_LOGIC;
                 signal clock_1_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_1_in_reset_n : OUT STD_LOGIC;
                 signal clock_1_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_1_in_write : OUT STD_LOGIC;
                 signal clock_1_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_0_data_master_granted_clock_1_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_1_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_1_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_1_in : OUT STD_LOGIC;
                 signal d1_clock_1_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_1_in_arbitrator : entity is FALSE;
end entity clock_1_in_arbitrator;


architecture europa of clock_1_in_arbitrator is
                signal clock_1_in_allgrants :  STD_LOGIC;
                signal clock_1_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_1_in_any_bursting_master_saved_grant :  STD_LOGIC;
                signal clock_1_in_any_continuerequest :  STD_LOGIC;
                signal clock_1_in_arb_counter_enable :  STD_LOGIC;
                signal clock_1_in_arb_share_counter :  STD_LOGIC;
                signal clock_1_in_arb_share_counter_next_value :  STD_LOGIC;
                signal clock_1_in_arb_share_set_values :  STD_LOGIC;
                signal clock_1_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_1_in_begins_xfer :  STD_LOGIC;
                signal clock_1_in_end_xfer :  STD_LOGIC;
                signal clock_1_in_firsttransfer :  STD_LOGIC;
                signal clock_1_in_grant_vector :  STD_LOGIC;
                signal clock_1_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_1_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_1_in_master_qreq_vector :  STD_LOGIC;
                signal clock_1_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_1_in_pretend_byte_enable :  STD_LOGIC;
                signal clock_1_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_1_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_1_in_waits_for_read :  STD_LOGIC;
                signal clock_1_in_waits_for_write :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_clock_1_in :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_clock_1_in :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_1_in_waitrequest_from_sa :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_clock_1_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_clock_1_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_clock_1_in :  STD_LOGIC;
                signal shifted_address_to_clock_1_in_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_clock_1_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_1_in_end_xfer;
      end if;
    end if;

  end process;

  clock_1_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_clock_1_in);
  --assign clock_1_in_readdata_from_sa = clock_1_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_1_in_readdata_from_sa <= clock_1_in_readdata;
  internal_cpu_0_data_master_requests_clock_1_in <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000100000100000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --assign clock_1_in_waitrequest_from_sa = clock_1_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_1_in_waitrequest_from_sa <= clock_1_in_waitrequest;
  --clock_1_in_arb_share_counter set values, which is an e_mux
  clock_1_in_arb_share_set_values <= std_logic'('1');
  --clock_1_in_non_bursting_master_requests mux, which is an e_mux
  clock_1_in_non_bursting_master_requests <= internal_cpu_0_data_master_requests_clock_1_in;
  --clock_1_in_any_bursting_master_saved_grant mux, which is an e_mux
  clock_1_in_any_bursting_master_saved_grant <= std_logic'('0');
  --clock_1_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_1_in_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(clock_1_in_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_in_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(clock_1_in_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_in_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --clock_1_in_allgrants all slave grants, which is an e_mux
  clock_1_in_allgrants <= clock_1_in_grant_vector;
  --clock_1_in_end_xfer assignment, which is an e_assign
  clock_1_in_end_xfer <= NOT ((clock_1_in_waits_for_read OR clock_1_in_waits_for_write));
  --end_xfer_arb_share_counter_term_clock_1_in arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_clock_1_in <= clock_1_in_end_xfer AND (((NOT clock_1_in_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --clock_1_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_1_in_arb_counter_enable <= ((end_xfer_arb_share_counter_term_clock_1_in AND clock_1_in_allgrants)) OR ((end_xfer_arb_share_counter_term_clock_1_in AND NOT clock_1_in_non_bursting_master_requests));
  --clock_1_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_1_in_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clock_1_in_arb_counter_enable) = '1' then 
        clock_1_in_arb_share_counter <= clock_1_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_1_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_1_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_1_in_master_qreq_vector AND end_xfer_arb_share_counter_term_clock_1_in)) OR ((end_xfer_arb_share_counter_term_clock_1_in AND NOT clock_1_in_non_bursting_master_requests)))) = '1' then 
        clock_1_in_slavearbiterlockenable <= clock_1_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master clock_1/in arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= clock_1_in_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --clock_1_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_1_in_slavearbiterlockenable2 <= clock_1_in_arb_share_counter_next_value;
  --cpu_0/data_master clock_1/in arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= clock_1_in_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --clock_1_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_1_in_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_clock_1_in <= internal_cpu_0_data_master_requests_clock_1_in AND NOT ((((cpu_0_data_master_read AND (NOT cpu_0_data_master_waitrequest))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))));
  --clock_1_in_writedata mux, which is an e_mux
  clock_1_in_writedata <= cpu_0_data_master_writedata (7 DOWNTO 0);
  --assign clock_1_in_endofpacket_from_sa = clock_1_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_1_in_endofpacket_from_sa <= clock_1_in_endofpacket;
  --master is always granted when requested
  internal_cpu_0_data_master_granted_clock_1_in <= internal_cpu_0_data_master_qualified_request_clock_1_in;
  --cpu_0/data_master saved-grant clock_1/in, which is an e_assign
  cpu_0_data_master_saved_grant_clock_1_in <= internal_cpu_0_data_master_requests_clock_1_in;
  --allow new arb cycle for clock_1/in, which is an e_assign
  clock_1_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_1_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_1_in_master_qreq_vector <= std_logic'('1');
  --clock_1_in_reset_n assignment, which is an e_assign
  clock_1_in_reset_n <= reset_n;
  --clock_1_in_firsttransfer first transaction, which is an e_assign
  clock_1_in_firsttransfer <= NOT ((clock_1_in_slavearbiterlockenable AND clock_1_in_any_continuerequest));
  --clock_1_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_1_in_beginbursttransfer_internal <= clock_1_in_begins_xfer;
  --clock_1_in_read assignment, which is an e_mux
  clock_1_in_read <= internal_cpu_0_data_master_granted_clock_1_in AND cpu_0_data_master_read;
  --clock_1_in_write assignment, which is an e_mux
  clock_1_in_write <= ((internal_cpu_0_data_master_granted_clock_1_in AND cpu_0_data_master_write)) AND clock_1_in_pretend_byte_enable;
  shifted_address_to_clock_1_in_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --clock_1_in_address mux, which is an e_mux
  clock_1_in_address <= A_EXT (A_SRL(shifted_address_to_clock_1_in_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --slaveid clock_1_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_1_in_nativeaddress <= A_EXT (A_SRL(cpu_0_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_clock_1_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_1_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_1_in_end_xfer <= clock_1_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_1_in_waits_for_read in a cycle, which is an e_mux
  clock_1_in_waits_for_read <= clock_1_in_in_a_read_cycle AND internal_clock_1_in_waitrequest_from_sa;
  --clock_1_in_in_a_read_cycle assignment, which is an e_assign
  clock_1_in_in_a_read_cycle <= internal_cpu_0_data_master_granted_clock_1_in AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_1_in_in_a_read_cycle;
  --clock_1_in_waits_for_write in a cycle, which is an e_mux
  clock_1_in_waits_for_write <= clock_1_in_in_a_write_cycle AND internal_clock_1_in_waitrequest_from_sa;
  --clock_1_in_in_a_write_cycle assignment, which is an e_assign
  clock_1_in_in_a_write_cycle <= internal_cpu_0_data_master_granted_clock_1_in AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_1_in_in_a_write_cycle;
  wait_for_clock_1_in_counter <= std_logic'('0');
  --clock_1_in_pretend_byte_enable byte enable port mux, which is an e_mux
  clock_1_in_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_clock_1_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  clock_1_in_waitrequest_from_sa <= internal_clock_1_in_waitrequest_from_sa;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_clock_1_in <= internal_cpu_0_data_master_granted_clock_1_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_clock_1_in <= internal_cpu_0_data_master_qualified_request_clock_1_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_clock_1_in <= internal_cpu_0_data_master_requests_clock_1_in;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_1_out_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_1_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_out_granted_rcv_data_s1 : IN STD_LOGIC;
                 signal clock_1_out_qualified_request_rcv_data_s1 : IN STD_LOGIC;
                 signal clock_1_out_read : IN STD_LOGIC;
                 signal clock_1_out_read_data_valid_rcv_data_s1 : IN STD_LOGIC;
                 signal clock_1_out_requests_rcv_data_s1 : IN STD_LOGIC;
                 signal clock_1_out_write : IN STD_LOGIC;
                 signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal d1_rcv_data_s1_end_xfer : IN STD_LOGIC;
                 signal rcv_data_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_1_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_1_out_reset_n : OUT STD_LOGIC;
                 signal clock_1_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_1_out_arbitrator : entity is FALSE;
end entity clock_1_out_arbitrator;


architecture europa of clock_1_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_1_out_address_last_time :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_read_last_time :  STD_LOGIC;
                signal clock_1_out_run :  STD_LOGIC;
                signal clock_1_out_write_last_time :  STD_LOGIC;
                signal clock_1_out_writedata_last_time :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal internal_clock_1_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_clock_1_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_1_out_qualified_request_rcv_data_s1 OR NOT clock_1_out_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_rcv_data_s1_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_1_out_qualified_request_rcv_data_s1 OR NOT clock_1_out_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_1_out_write)))))))));
  --cascaded wait assignment, which is an e_assign
  clock_1_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_1_out_address_to_slave <= clock_1_out_address;
  --clock_1/out readdata mux, which is an e_mux
  clock_1_out_readdata <= std_logic_vector'("0000") & (rcv_data_s1_readdata_from_sa);
  --actual waitrequest port, which is an e_assign
  internal_clock_1_out_waitrequest <= NOT clock_1_out_run;
  --clock_1_out_reset_n assignment, which is an e_assign
  clock_1_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_1_out_address_to_slave <= internal_clock_1_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_1_out_waitrequest <= internal_clock_1_out_waitrequest;
--synthesis translate_off
    --clock_1_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_address_last_time <= std_logic_vector'("00");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_address_last_time <= clock_1_out_address;
        end if;
      end if;

    end process;

    --clock_1/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_1_out_waitrequest AND ((clock_1_out_read OR clock_1_out_write));
        end if;
      end if;

    end process;

    --clock_1_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_address, clock_1_out_address_last_time)
    VARIABLE write_line4 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_1_out_address /= clock_1_out_address_last_time))))) = '1' then 
          write(write_line4, now);
          write(write_line4, string'(": "));
          write(write_line4, string'("clock_1_out_address did not heed wait!!!"));
          write(output, write_line4.all);
          deallocate (write_line4);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_read_last_time <= clock_1_out_read;
        end if;
      end if;

    end process;

    --clock_1_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_read, clock_1_out_read_last_time)
    VARIABLE write_line5 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_1_out_read) /= std_logic'(clock_1_out_read_last_time)))))) = '1' then 
          write(write_line5, now);
          write(write_line5, string'(": "));
          write(write_line5, string'("clock_1_out_read did not heed wait!!!"));
          write(output, write_line5.all);
          deallocate (write_line5);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_write_last_time <= clock_1_out_write;
        end if;
      end if;

    end process;

    --clock_1_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_write, clock_1_out_write_last_time)
    VARIABLE write_line6 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_1_out_write) /= std_logic'(clock_1_out_write_last_time)))))) = '1' then 
          write(write_line6, now);
          write(write_line6, string'(": "));
          write(write_line6, string'("clock_1_out_write did not heed wait!!!"));
          write(output, write_line6.all);
          deallocate (write_line6);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_1_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_1_out_writedata_last_time <= std_logic_vector'("00000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_1_out_writedata_last_time <= clock_1_out_writedata;
        end if;
      end if;

    end process;

    --clock_1_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_1_out_write, clock_1_out_writedata, clock_1_out_writedata_last_time)
    VARIABLE write_line7 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_1_out_writedata /= clock_1_out_writedata_last_time)))) AND clock_1_out_write)) = '1' then 
          write(write_line7, now);
          write(write_line7, string'(": "));
          write(write_line7, string'("clock_1_out_writedata did not heed wait!!!"));
          write(output, write_line7.all);
          deallocate (write_line7);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_2_in_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_2_in_endofpacket : IN STD_LOGIC;
                 signal clock_2_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_2_in_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_2_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_2_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_in_read : OUT STD_LOGIC;
                 signal clock_2_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_2_in_reset_n : OUT STD_LOGIC;
                 signal clock_2_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_2_in_write : OUT STD_LOGIC;
                 signal clock_2_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_0_data_master_granted_clock_2_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_2_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_2_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_2_in : OUT STD_LOGIC;
                 signal d1_clock_2_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_2_in_arbitrator : entity is FALSE;
end entity clock_2_in_arbitrator;


architecture europa of clock_2_in_arbitrator is
                signal clock_2_in_allgrants :  STD_LOGIC;
                signal clock_2_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_2_in_any_bursting_master_saved_grant :  STD_LOGIC;
                signal clock_2_in_any_continuerequest :  STD_LOGIC;
                signal clock_2_in_arb_counter_enable :  STD_LOGIC;
                signal clock_2_in_arb_share_counter :  STD_LOGIC;
                signal clock_2_in_arb_share_counter_next_value :  STD_LOGIC;
                signal clock_2_in_arb_share_set_values :  STD_LOGIC;
                signal clock_2_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_2_in_begins_xfer :  STD_LOGIC;
                signal clock_2_in_end_xfer :  STD_LOGIC;
                signal clock_2_in_firsttransfer :  STD_LOGIC;
                signal clock_2_in_grant_vector :  STD_LOGIC;
                signal clock_2_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_2_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_2_in_master_qreq_vector :  STD_LOGIC;
                signal clock_2_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_2_in_pretend_byte_enable :  STD_LOGIC;
                signal clock_2_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_2_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_2_in_waits_for_read :  STD_LOGIC;
                signal clock_2_in_waits_for_write :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_clock_2_in :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_clock_2_in :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_2_in_waitrequest_from_sa :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_clock_2_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_clock_2_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_clock_2_in :  STD_LOGIC;
                signal shifted_address_to_clock_2_in_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_clock_2_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_2_in_end_xfer;
      end if;
    end if;

  end process;

  clock_2_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_clock_2_in);
  --assign clock_2_in_readdata_from_sa = clock_2_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_2_in_readdata_from_sa <= clock_2_in_readdata;
  internal_cpu_0_data_master_requests_clock_2_in <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000100000110000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --assign clock_2_in_waitrequest_from_sa = clock_2_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_2_in_waitrequest_from_sa <= clock_2_in_waitrequest;
  --clock_2_in_arb_share_counter set values, which is an e_mux
  clock_2_in_arb_share_set_values <= std_logic'('1');
  --clock_2_in_non_bursting_master_requests mux, which is an e_mux
  clock_2_in_non_bursting_master_requests <= internal_cpu_0_data_master_requests_clock_2_in;
  --clock_2_in_any_bursting_master_saved_grant mux, which is an e_mux
  clock_2_in_any_bursting_master_saved_grant <= std_logic'('0');
  --clock_2_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_2_in_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(clock_2_in_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_2_in_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(clock_2_in_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_2_in_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --clock_2_in_allgrants all slave grants, which is an e_mux
  clock_2_in_allgrants <= clock_2_in_grant_vector;
  --clock_2_in_end_xfer assignment, which is an e_assign
  clock_2_in_end_xfer <= NOT ((clock_2_in_waits_for_read OR clock_2_in_waits_for_write));
  --end_xfer_arb_share_counter_term_clock_2_in arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_clock_2_in <= clock_2_in_end_xfer AND (((NOT clock_2_in_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --clock_2_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_2_in_arb_counter_enable <= ((end_xfer_arb_share_counter_term_clock_2_in AND clock_2_in_allgrants)) OR ((end_xfer_arb_share_counter_term_clock_2_in AND NOT clock_2_in_non_bursting_master_requests));
  --clock_2_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_2_in_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clock_2_in_arb_counter_enable) = '1' then 
        clock_2_in_arb_share_counter <= clock_2_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_2_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_2_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_2_in_master_qreq_vector AND end_xfer_arb_share_counter_term_clock_2_in)) OR ((end_xfer_arb_share_counter_term_clock_2_in AND NOT clock_2_in_non_bursting_master_requests)))) = '1' then 
        clock_2_in_slavearbiterlockenable <= clock_2_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master clock_2/in arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= clock_2_in_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --clock_2_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_2_in_slavearbiterlockenable2 <= clock_2_in_arb_share_counter_next_value;
  --cpu_0/data_master clock_2/in arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= clock_2_in_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --clock_2_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_2_in_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_clock_2_in <= internal_cpu_0_data_master_requests_clock_2_in AND NOT ((((cpu_0_data_master_read AND (NOT cpu_0_data_master_waitrequest))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))));
  --clock_2_in_writedata mux, which is an e_mux
  clock_2_in_writedata <= cpu_0_data_master_writedata (7 DOWNTO 0);
  --assign clock_2_in_endofpacket_from_sa = clock_2_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_2_in_endofpacket_from_sa <= clock_2_in_endofpacket;
  --master is always granted when requested
  internal_cpu_0_data_master_granted_clock_2_in <= internal_cpu_0_data_master_qualified_request_clock_2_in;
  --cpu_0/data_master saved-grant clock_2/in, which is an e_assign
  cpu_0_data_master_saved_grant_clock_2_in <= internal_cpu_0_data_master_requests_clock_2_in;
  --allow new arb cycle for clock_2/in, which is an e_assign
  clock_2_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_2_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_2_in_master_qreq_vector <= std_logic'('1');
  --clock_2_in_reset_n assignment, which is an e_assign
  clock_2_in_reset_n <= reset_n;
  --clock_2_in_firsttransfer first transaction, which is an e_assign
  clock_2_in_firsttransfer <= NOT ((clock_2_in_slavearbiterlockenable AND clock_2_in_any_continuerequest));
  --clock_2_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_2_in_beginbursttransfer_internal <= clock_2_in_begins_xfer;
  --clock_2_in_read assignment, which is an e_mux
  clock_2_in_read <= internal_cpu_0_data_master_granted_clock_2_in AND cpu_0_data_master_read;
  --clock_2_in_write assignment, which is an e_mux
  clock_2_in_write <= ((internal_cpu_0_data_master_granted_clock_2_in AND cpu_0_data_master_write)) AND clock_2_in_pretend_byte_enable;
  shifted_address_to_clock_2_in_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --clock_2_in_address mux, which is an e_mux
  clock_2_in_address <= A_EXT (A_SRL(shifted_address_to_clock_2_in_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --slaveid clock_2_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_2_in_nativeaddress <= A_EXT (A_SRL(cpu_0_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_clock_2_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_2_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_2_in_end_xfer <= clock_2_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_2_in_waits_for_read in a cycle, which is an e_mux
  clock_2_in_waits_for_read <= clock_2_in_in_a_read_cycle AND internal_clock_2_in_waitrequest_from_sa;
  --clock_2_in_in_a_read_cycle assignment, which is an e_assign
  clock_2_in_in_a_read_cycle <= internal_cpu_0_data_master_granted_clock_2_in AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_2_in_in_a_read_cycle;
  --clock_2_in_waits_for_write in a cycle, which is an e_mux
  clock_2_in_waits_for_write <= clock_2_in_in_a_write_cycle AND internal_clock_2_in_waitrequest_from_sa;
  --clock_2_in_in_a_write_cycle assignment, which is an e_assign
  clock_2_in_in_a_write_cycle <= internal_cpu_0_data_master_granted_clock_2_in AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_2_in_in_a_write_cycle;
  wait_for_clock_2_in_counter <= std_logic'('0');
  --clock_2_in_pretend_byte_enable byte enable port mux, which is an e_mux
  clock_2_in_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_clock_2_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  clock_2_in_waitrequest_from_sa <= internal_clock_2_in_waitrequest_from_sa;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_clock_2_in <= internal_cpu_0_data_master_granted_clock_2_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_clock_2_in <= internal_cpu_0_data_master_qualified_request_clock_2_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_clock_2_in <= internal_cpu_0_data_master_requests_clock_2_in;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_2_out_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_2_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_out_granted_xmt_dv_s1 : IN STD_LOGIC;
                 signal clock_2_out_qualified_request_xmt_dv_s1 : IN STD_LOGIC;
                 signal clock_2_out_read : IN STD_LOGIC;
                 signal clock_2_out_read_data_valid_xmt_dv_s1 : IN STD_LOGIC;
                 signal clock_2_out_requests_xmt_dv_s1 : IN STD_LOGIC;
                 signal clock_2_out_write : IN STD_LOGIC;
                 signal clock_2_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal d1_xmt_dv_s1_end_xfer : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_2_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_2_out_reset_n : OUT STD_LOGIC;
                 signal clock_2_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_2_out_arbitrator : entity is FALSE;
end entity clock_2_out_arbitrator;


architecture europa of clock_2_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_2_out_address_last_time :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_out_read_last_time :  STD_LOGIC;
                signal clock_2_out_run :  STD_LOGIC;
                signal clock_2_out_write_last_time :  STD_LOGIC;
                signal clock_2_out_writedata_last_time :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal internal_clock_2_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_clock_2_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_2_out_qualified_request_xmt_dv_s1 OR NOT clock_2_out_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_xmt_dv_s1_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_2_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_2_out_qualified_request_xmt_dv_s1 OR NOT clock_2_out_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_2_out_write)))))))));
  --cascaded wait assignment, which is an e_assign
  clock_2_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_2_out_address_to_slave <= clock_2_out_address;
  --actual waitrequest port, which is an e_assign
  internal_clock_2_out_waitrequest <= NOT clock_2_out_run;
  --clock_2_out_reset_n assignment, which is an e_assign
  clock_2_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_2_out_address_to_slave <= internal_clock_2_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_2_out_waitrequest <= internal_clock_2_out_waitrequest;
--synthesis translate_off
    --clock_2_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_2_out_address_last_time <= std_logic_vector'("00");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_2_out_address_last_time <= clock_2_out_address;
        end if;
      end if;

    end process;

    --clock_2/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_2_out_waitrequest AND ((clock_2_out_read OR clock_2_out_write));
        end if;
      end if;

    end process;

    --clock_2_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_2_out_address, clock_2_out_address_last_time)
    VARIABLE write_line8 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_2_out_address /= clock_2_out_address_last_time))))) = '1' then 
          write(write_line8, now);
          write(write_line8, string'(": "));
          write(write_line8, string'("clock_2_out_address did not heed wait!!!"));
          write(output, write_line8.all);
          deallocate (write_line8);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_2_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_2_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_2_out_read_last_time <= clock_2_out_read;
        end if;
      end if;

    end process;

    --clock_2_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_2_out_read, clock_2_out_read_last_time)
    VARIABLE write_line9 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_2_out_read) /= std_logic'(clock_2_out_read_last_time)))))) = '1' then 
          write(write_line9, now);
          write(write_line9, string'(": "));
          write(write_line9, string'("clock_2_out_read did not heed wait!!!"));
          write(output, write_line9.all);
          deallocate (write_line9);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_2_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_2_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_2_out_write_last_time <= clock_2_out_write;
        end if;
      end if;

    end process;

    --clock_2_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_2_out_write, clock_2_out_write_last_time)
    VARIABLE write_line10 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_2_out_write) /= std_logic'(clock_2_out_write_last_time)))))) = '1' then 
          write(write_line10, now);
          write(write_line10, string'(": "));
          write(write_line10, string'("clock_2_out_write did not heed wait!!!"));
          write(output, write_line10.all);
          deallocate (write_line10);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_2_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_2_out_writedata_last_time <= std_logic_vector'("00000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_2_out_writedata_last_time <= clock_2_out_writedata;
        end if;
      end if;

    end process;

    --clock_2_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_2_out_write, clock_2_out_writedata, clock_2_out_writedata_last_time)
    VARIABLE write_line11 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_2_out_writedata /= clock_2_out_writedata_last_time)))) AND clock_2_out_write)) = '1' then 
          write(write_line11, now);
          write(write_line11, string'(": "));
          write(write_line11, string'("clock_2_out_writedata did not heed wait!!!"));
          write(output, write_line11.all);
          deallocate (write_line11);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_3_in_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_3_in_endofpacket : IN STD_LOGIC;
                 signal clock_3_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_3_in_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_3_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_in_endofpacket_from_sa : OUT STD_LOGIC;
                 signal clock_3_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_in_read : OUT STD_LOGIC;
                 signal clock_3_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_3_in_reset_n : OUT STD_LOGIC;
                 signal clock_3_in_waitrequest_from_sa : OUT STD_LOGIC;
                 signal clock_3_in_write : OUT STD_LOGIC;
                 signal clock_3_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal cpu_0_data_master_granted_clock_3_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_3_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_3_in : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_3_in : OUT STD_LOGIC;
                 signal d1_clock_3_in_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_3_in_arbitrator : entity is FALSE;
end entity clock_3_in_arbitrator;


architecture europa of clock_3_in_arbitrator is
                signal clock_3_in_allgrants :  STD_LOGIC;
                signal clock_3_in_allow_new_arb_cycle :  STD_LOGIC;
                signal clock_3_in_any_bursting_master_saved_grant :  STD_LOGIC;
                signal clock_3_in_any_continuerequest :  STD_LOGIC;
                signal clock_3_in_arb_counter_enable :  STD_LOGIC;
                signal clock_3_in_arb_share_counter :  STD_LOGIC;
                signal clock_3_in_arb_share_counter_next_value :  STD_LOGIC;
                signal clock_3_in_arb_share_set_values :  STD_LOGIC;
                signal clock_3_in_beginbursttransfer_internal :  STD_LOGIC;
                signal clock_3_in_begins_xfer :  STD_LOGIC;
                signal clock_3_in_end_xfer :  STD_LOGIC;
                signal clock_3_in_firsttransfer :  STD_LOGIC;
                signal clock_3_in_grant_vector :  STD_LOGIC;
                signal clock_3_in_in_a_read_cycle :  STD_LOGIC;
                signal clock_3_in_in_a_write_cycle :  STD_LOGIC;
                signal clock_3_in_master_qreq_vector :  STD_LOGIC;
                signal clock_3_in_non_bursting_master_requests :  STD_LOGIC;
                signal clock_3_in_pretend_byte_enable :  STD_LOGIC;
                signal clock_3_in_slavearbiterlockenable :  STD_LOGIC;
                signal clock_3_in_slavearbiterlockenable2 :  STD_LOGIC;
                signal clock_3_in_waits_for_read :  STD_LOGIC;
                signal clock_3_in_waits_for_write :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_clock_3_in :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_clock_3_in :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_3_in_waitrequest_from_sa :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_clock_3_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_clock_3_in :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_clock_3_in :  STD_LOGIC;
                signal shifted_address_to_clock_3_in_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_clock_3_in_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT clock_3_in_end_xfer;
      end if;
    end if;

  end process;

  clock_3_in_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_clock_3_in);
  --assign clock_3_in_readdata_from_sa = clock_3_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_3_in_readdata_from_sa <= clock_3_in_readdata;
  internal_cpu_0_data_master_requests_clock_3_in <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000100001000000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --assign clock_3_in_waitrequest_from_sa = clock_3_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_clock_3_in_waitrequest_from_sa <= clock_3_in_waitrequest;
  --clock_3_in_arb_share_counter set values, which is an e_mux
  clock_3_in_arb_share_set_values <= std_logic'('1');
  --clock_3_in_non_bursting_master_requests mux, which is an e_mux
  clock_3_in_non_bursting_master_requests <= internal_cpu_0_data_master_requests_clock_3_in;
  --clock_3_in_any_bursting_master_saved_grant mux, which is an e_mux
  clock_3_in_any_bursting_master_saved_grant <= std_logic'('0');
  --clock_3_in_arb_share_counter_next_value assignment, which is an e_assign
  clock_3_in_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(clock_3_in_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_3_in_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(clock_3_in_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_3_in_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --clock_3_in_allgrants all slave grants, which is an e_mux
  clock_3_in_allgrants <= clock_3_in_grant_vector;
  --clock_3_in_end_xfer assignment, which is an e_assign
  clock_3_in_end_xfer <= NOT ((clock_3_in_waits_for_read OR clock_3_in_waits_for_write));
  --end_xfer_arb_share_counter_term_clock_3_in arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_clock_3_in <= clock_3_in_end_xfer AND (((NOT clock_3_in_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --clock_3_in_arb_share_counter arbitration counter enable, which is an e_assign
  clock_3_in_arb_counter_enable <= ((end_xfer_arb_share_counter_term_clock_3_in AND clock_3_in_allgrants)) OR ((end_xfer_arb_share_counter_term_clock_3_in AND NOT clock_3_in_non_bursting_master_requests));
  --clock_3_in_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_3_in_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(clock_3_in_arb_counter_enable) = '1' then 
        clock_3_in_arb_share_counter <= clock_3_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_3_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      clock_3_in_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((clock_3_in_master_qreq_vector AND end_xfer_arb_share_counter_term_clock_3_in)) OR ((end_xfer_arb_share_counter_term_clock_3_in AND NOT clock_3_in_non_bursting_master_requests)))) = '1' then 
        clock_3_in_slavearbiterlockenable <= clock_3_in_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master clock_3/in arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= clock_3_in_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --clock_3_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  clock_3_in_slavearbiterlockenable2 <= clock_3_in_arb_share_counter_next_value;
  --cpu_0/data_master clock_3/in arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= clock_3_in_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --clock_3_in_any_continuerequest at least one master continues requesting, which is an e_assign
  clock_3_in_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_clock_3_in <= internal_cpu_0_data_master_requests_clock_3_in AND NOT ((((cpu_0_data_master_read AND (NOT cpu_0_data_master_waitrequest))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))));
  --clock_3_in_writedata mux, which is an e_mux
  clock_3_in_writedata <= cpu_0_data_master_writedata (7 DOWNTO 0);
  --assign clock_3_in_endofpacket_from_sa = clock_3_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  clock_3_in_endofpacket_from_sa <= clock_3_in_endofpacket;
  --master is always granted when requested
  internal_cpu_0_data_master_granted_clock_3_in <= internal_cpu_0_data_master_qualified_request_clock_3_in;
  --cpu_0/data_master saved-grant clock_3/in, which is an e_assign
  cpu_0_data_master_saved_grant_clock_3_in <= internal_cpu_0_data_master_requests_clock_3_in;
  --allow new arb cycle for clock_3/in, which is an e_assign
  clock_3_in_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  clock_3_in_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  clock_3_in_master_qreq_vector <= std_logic'('1');
  --clock_3_in_reset_n assignment, which is an e_assign
  clock_3_in_reset_n <= reset_n;
  --clock_3_in_firsttransfer first transaction, which is an e_assign
  clock_3_in_firsttransfer <= NOT ((clock_3_in_slavearbiterlockenable AND clock_3_in_any_continuerequest));
  --clock_3_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
  clock_3_in_beginbursttransfer_internal <= clock_3_in_begins_xfer;
  --clock_3_in_read assignment, which is an e_mux
  clock_3_in_read <= internal_cpu_0_data_master_granted_clock_3_in AND cpu_0_data_master_read;
  --clock_3_in_write assignment, which is an e_mux
  clock_3_in_write <= ((internal_cpu_0_data_master_granted_clock_3_in AND cpu_0_data_master_write)) AND clock_3_in_pretend_byte_enable;
  shifted_address_to_clock_3_in_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --clock_3_in_address mux, which is an e_mux
  clock_3_in_address <= A_EXT (A_SRL(shifted_address_to_clock_3_in_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --slaveid clock_3_in_nativeaddress nativeaddress mux, which is an e_mux
  clock_3_in_nativeaddress <= A_EXT (A_SRL(cpu_0_data_master_address_to_slave,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_clock_3_in_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_clock_3_in_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_clock_3_in_end_xfer <= clock_3_in_end_xfer;
      end if;
    end if;

  end process;

  --clock_3_in_waits_for_read in a cycle, which is an e_mux
  clock_3_in_waits_for_read <= clock_3_in_in_a_read_cycle AND internal_clock_3_in_waitrequest_from_sa;
  --clock_3_in_in_a_read_cycle assignment, which is an e_assign
  clock_3_in_in_a_read_cycle <= internal_cpu_0_data_master_granted_clock_3_in AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= clock_3_in_in_a_read_cycle;
  --clock_3_in_waits_for_write in a cycle, which is an e_mux
  clock_3_in_waits_for_write <= clock_3_in_in_a_write_cycle AND internal_clock_3_in_waitrequest_from_sa;
  --clock_3_in_in_a_write_cycle assignment, which is an e_assign
  clock_3_in_in_a_write_cycle <= internal_cpu_0_data_master_granted_clock_3_in AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= clock_3_in_in_a_write_cycle;
  wait_for_clock_3_in_counter <= std_logic'('0');
  --clock_3_in_pretend_byte_enable byte enable port mux, which is an e_mux
  clock_3_in_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_clock_3_in)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  clock_3_in_waitrequest_from_sa <= internal_clock_3_in_waitrequest_from_sa;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_clock_3_in <= internal_cpu_0_data_master_granted_clock_3_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_clock_3_in <= internal_cpu_0_data_master_qualified_request_clock_3_in;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_clock_3_in <= internal_cpu_0_data_master_requests_clock_3_in;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity clock_3_out_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_3_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_out_granted_xmt_data_s1 : IN STD_LOGIC;
                 signal clock_3_out_qualified_request_xmt_data_s1 : IN STD_LOGIC;
                 signal clock_3_out_read : IN STD_LOGIC;
                 signal clock_3_out_read_data_valid_xmt_data_s1 : IN STD_LOGIC;
                 signal clock_3_out_requests_xmt_data_s1 : IN STD_LOGIC;
                 signal clock_3_out_write : IN STD_LOGIC;
                 signal clock_3_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal d1_xmt_data_s1_end_xfer : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_3_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_3_out_reset_n : OUT STD_LOGIC;
                 signal clock_3_out_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of clock_3_out_arbitrator : entity is FALSE;
end entity clock_3_out_arbitrator;


architecture europa of clock_3_out_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal clock_3_out_address_last_time :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_out_read_last_time :  STD_LOGIC;
                signal clock_3_out_run :  STD_LOGIC;
                signal clock_3_out_write_last_time :  STD_LOGIC;
                signal clock_3_out_writedata_last_time :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal internal_clock_3_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_clock_3_out_waitrequest :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_3_out_qualified_request_xmt_data_s1 OR NOT clock_3_out_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_xmt_data_s1_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_3_out_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT clock_3_out_qualified_request_xmt_data_s1 OR NOT clock_3_out_write)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_3_out_write)))))))));
  --cascaded wait assignment, which is an e_assign
  clock_3_out_run <= r_1;
  --optimize select-logic by passing only those address bits which matter.
  internal_clock_3_out_address_to_slave <= clock_3_out_address;
  --actual waitrequest port, which is an e_assign
  internal_clock_3_out_waitrequest <= NOT clock_3_out_run;
  --clock_3_out_reset_n assignment, which is an e_assign
  clock_3_out_reset_n <= reset_n;
  --vhdl renameroo for output signals
  clock_3_out_address_to_slave <= internal_clock_3_out_address_to_slave;
  --vhdl renameroo for output signals
  clock_3_out_waitrequest <= internal_clock_3_out_waitrequest;
--synthesis translate_off
    --clock_3_out_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_3_out_address_last_time <= std_logic_vector'("00");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_3_out_address_last_time <= clock_3_out_address;
        end if;
      end if;

    end process;

    --clock_3/out waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_clock_3_out_waitrequest AND ((clock_3_out_read OR clock_3_out_write));
        end if;
      end if;

    end process;

    --clock_3_out_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_3_out_address, clock_3_out_address_last_time)
    VARIABLE write_line12 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((clock_3_out_address /= clock_3_out_address_last_time))))) = '1' then 
          write(write_line12, now);
          write(write_line12, string'(": "));
          write(write_line12, string'("clock_3_out_address did not heed wait!!!"));
          write(output, write_line12.all);
          deallocate (write_line12);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_3_out_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_3_out_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_3_out_read_last_time <= clock_3_out_read;
        end if;
      end if;

    end process;

    --clock_3_out_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_3_out_read, clock_3_out_read_last_time)
    VARIABLE write_line13 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_3_out_read) /= std_logic'(clock_3_out_read_last_time)))))) = '1' then 
          write(write_line13, now);
          write(write_line13, string'(": "));
          write(write_line13, string'("clock_3_out_read did not heed wait!!!"));
          write(output, write_line13.all);
          deallocate (write_line13);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_3_out_write check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_3_out_write_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_3_out_write_last_time <= clock_3_out_write;
        end if;
      end if;

    end process;

    --clock_3_out_write matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_3_out_write, clock_3_out_write_last_time)
    VARIABLE write_line14 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(clock_3_out_write) /= std_logic'(clock_3_out_write_last_time)))))) = '1' then 
          write(write_line14, now);
          write(write_line14, string'(": "));
          write(write_line14, string'("clock_3_out_write did not heed wait!!!"));
          write(output, write_line14.all);
          deallocate (write_line14);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --clock_3_out_writedata check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        clock_3_out_writedata_last_time <= std_logic_vector'("00000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          clock_3_out_writedata_last_time <= clock_3_out_writedata;
        end if;
      end if;

    end process;

    --clock_3_out_writedata matches last port_name, which is an e_process
    process (active_and_waiting_last_time, clock_3_out_write, clock_3_out_writedata, clock_3_out_writedata_last_time)
    VARIABLE write_line15 : line;
    begin
        if std_logic'(((active_and_waiting_last_time AND to_std_logic(((clock_3_out_writedata /= clock_3_out_writedata_last_time)))) AND clock_3_out_write)) = '1' then 
          write(write_line15, now);
          write(write_line15, string'(": "));
          write(write_line15, string'("clock_3_out_writedata did not heed wait!!!"));
          write(output, write_line15.all);
          deallocate (write_line15);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity cpu_0_jtag_debug_module_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_debugaccess : IN STD_LOGIC;
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_instruction_master_latency_counter : IN STD_LOGIC;
                 signal cpu_0_instruction_master_read : IN STD_LOGIC;
                 signal cpu_0_jtag_debug_module_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_jtag_debug_module_resetrequest : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_granted_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_granted_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_requests_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal cpu_0_jtag_debug_module_begintransfer : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_jtag_debug_module_chipselect : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_debugaccess : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_jtag_debug_module_reset : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_resetrequest_from_sa : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_write : OUT STD_LOGIC;
                 signal cpu_0_jtag_debug_module_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_cpu_0_jtag_debug_module_end_xfer : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_0_jtag_debug_module_arbitrator : entity is FALSE;
end entity cpu_0_jtag_debug_module_arbitrator;


architecture europa of cpu_0_jtag_debug_module_arbitrator is
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_instruction_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_instruction_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_instruction_master_continuerequest :  STD_LOGIC;
                signal cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_allgrants :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_allow_new_arb_cycle :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_any_bursting_master_saved_grant :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_any_continuerequest :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_arb_counter_enable :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_arb_share_counter :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_arb_share_counter_next_value :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_arb_share_set_values :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_arbitration_holdoff_internal :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_beginbursttransfer_internal :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_begins_xfer :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal cpu_0_jtag_debug_module_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_end_xfer :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_firsttransfer :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_in_a_read_cycle :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_in_a_write_cycle :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_non_bursting_master_requests :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal cpu_0_jtag_debug_module_slavearbiterlockenable :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_slavearbiterlockenable2 :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_waits_for_read :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_waits_for_write :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_cpu_0_jtag_debug_module_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT cpu_0_jtag_debug_module_end_xfer;
      end if;
    end if;

  end process;

  cpu_0_jtag_debug_module_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module OR internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module));
  --assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  cpu_0_jtag_debug_module_readdata_from_sa <= cpu_0_jtag_debug_module_readdata;
  internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("100000000000000000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
  cpu_0_jtag_debug_module_arb_share_set_values <= std_logic'('1');
  --cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  cpu_0_jtag_debug_module_non_bursting_master_requests <= ((internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module OR internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) OR internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module) OR internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
  --cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  cpu_0_jtag_debug_module_any_bursting_master_saved_grant <= std_logic'('0');
  --cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  cpu_0_jtag_debug_module_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_0_jtag_debug_module_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_jtag_debug_module_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(cpu_0_jtag_debug_module_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_jtag_debug_module_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
  cpu_0_jtag_debug_module_allgrants <= ((or_reduce(cpu_0_jtag_debug_module_grant_vector) OR or_reduce(cpu_0_jtag_debug_module_grant_vector)) OR or_reduce(cpu_0_jtag_debug_module_grant_vector)) OR or_reduce(cpu_0_jtag_debug_module_grant_vector);
  --cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
  cpu_0_jtag_debug_module_end_xfer <= NOT ((cpu_0_jtag_debug_module_waits_for_read OR cpu_0_jtag_debug_module_waits_for_write));
  --end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_end_xfer AND (((NOT cpu_0_jtag_debug_module_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  cpu_0_jtag_debug_module_arb_counter_enable <= ((end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module AND cpu_0_jtag_debug_module_allgrants)) OR ((end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module AND NOT cpu_0_jtag_debug_module_non_bursting_master_requests));
  --cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_jtag_debug_module_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(cpu_0_jtag_debug_module_arb_counter_enable) = '1' then 
        cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_jtag_debug_module_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((or_reduce(cpu_0_jtag_debug_module_master_qreq_vector) AND end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module)) OR ((end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module AND NOT cpu_0_jtag_debug_module_non_bursting_master_requests)))) = '1' then 
        cpu_0_jtag_debug_module_slavearbiterlockenable <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= cpu_0_jtag_debug_module_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  cpu_0_jtag_debug_module_slavearbiterlockenable2 <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
  --cpu_0/data_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= cpu_0_jtag_debug_module_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  cpu_0_instruction_master_arbiterlock <= cpu_0_jtag_debug_module_slavearbiterlockenable AND cpu_0_instruction_master_continuerequest;
  --cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  cpu_0_instruction_master_arbiterlock2 <= cpu_0_jtag_debug_module_slavearbiterlockenable2 AND cpu_0_instruction_master_continuerequest;
  --cpu_0/instruction_master granted cpu_0/jtag_debug_module last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((cpu_0_jtag_debug_module_arbitration_holdoff_internal OR NOT internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module))))));
      end if;
    end if;

  end process;

  --cpu_0_instruction_master_continuerequest continued request, which is an e_mux
  cpu_0_instruction_master_continuerequest <= last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module AND internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
  --cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  cpu_0_jtag_debug_module_any_continuerequest <= cpu_0_instruction_master_continuerequest OR cpu_0_data_master_continuerequest;
  internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module AND NOT (cpu_0_instruction_master_arbiterlock);
  --cpu_0_jtag_debug_module_writedata mux, which is an e_mux
  cpu_0_jtag_debug_module_writedata <= cpu_0_data_master_writedata;
  --mux cpu_0_jtag_debug_module_debugaccess, which is an e_mux
  cpu_0_jtag_debug_module_debugaccess <= cpu_0_data_master_debugaccess;
  internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module <= ((to_std_logic(((Std_Logic_Vector'(cpu_0_instruction_master_address_to_slave(17 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("100000000000000000")))) AND (cpu_0_instruction_master_read))) AND cpu_0_instruction_master_read;
  --cpu_0/data_master granted cpu_0/jtag_debug_module last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((cpu_0_jtag_debug_module_arbitration_holdoff_internal OR NOT internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module))))));
      end if;
    end if;

  end process;

  --cpu_0_data_master_continuerequest continued request, which is an e_mux
  cpu_0_data_master_continuerequest <= last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module AND internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module AND NOT ((((cpu_0_instruction_master_read AND to_std_logic((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_latency_counter))) /= std_logic_vector'("00000000000000000000000000000000")))))) OR cpu_0_data_master_arbiterlock));
  --local readdatavalid cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module, which is an e_mux
  cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module <= (internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module AND cpu_0_instruction_master_read) AND NOT cpu_0_jtag_debug_module_waits_for_read;
  --allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
  cpu_0_jtag_debug_module_allow_new_arb_cycle <= NOT cpu_0_data_master_arbiterlock AND NOT cpu_0_instruction_master_arbiterlock;
  --cpu_0/instruction_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  cpu_0_jtag_debug_module_master_qreq_vector(0) <= internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
  --cpu_0/instruction_master grant cpu_0/jtag_debug_module, which is an e_assign
  internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector(0);
  --cpu_0/instruction_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
  cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_arb_winner(0) AND internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
  --cpu_0/data_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  cpu_0_jtag_debug_module_master_qreq_vector(1) <= internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  --cpu_0/data_master grant cpu_0/jtag_debug_module, which is an e_assign
  internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_grant_vector(1);
  --cpu_0/data_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
  cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module <= cpu_0_jtag_debug_module_arb_winner(1) AND internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  --cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
  cpu_0_jtag_debug_module_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((cpu_0_jtag_debug_module_master_qreq_vector & cpu_0_jtag_debug_module_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT cpu_0_jtag_debug_module_master_qreq_vector & NOT cpu_0_jtag_debug_module_master_qreq_vector))) + (std_logic_vector'("000") & (cpu_0_jtag_debug_module_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  cpu_0_jtag_debug_module_arb_winner <= A_WE_StdLogicVector((std_logic'(((cpu_0_jtag_debug_module_allow_new_arb_cycle AND or_reduce(cpu_0_jtag_debug_module_grant_vector)))) = '1'), cpu_0_jtag_debug_module_grant_vector, cpu_0_jtag_debug_module_saved_chosen_master_vector);
  --saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_jtag_debug_module_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(cpu_0_jtag_debug_module_allow_new_arb_cycle) = '1' then 
        cpu_0_jtag_debug_module_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(cpu_0_jtag_debug_module_grant_vector)) = '1'), cpu_0_jtag_debug_module_grant_vector, cpu_0_jtag_debug_module_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  cpu_0_jtag_debug_module_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((cpu_0_jtag_debug_module_chosen_master_double_vector(1) OR cpu_0_jtag_debug_module_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((cpu_0_jtag_debug_module_chosen_master_double_vector(0) OR cpu_0_jtag_debug_module_chosen_master_double_vector(2)))));
  --cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
  cpu_0_jtag_debug_module_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(cpu_0_jtag_debug_module_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(cpu_0_jtag_debug_module_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --cpu_0/jtag_debug_module's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_jtag_debug_module_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(cpu_0_jtag_debug_module_grant_vector)) = '1' then 
        cpu_0_jtag_debug_module_arb_addend <= A_WE_StdLogicVector((std_logic'(cpu_0_jtag_debug_module_end_xfer) = '1'), cpu_0_jtag_debug_module_chosen_master_rot_left, cpu_0_jtag_debug_module_grant_vector);
      end if;
    end if;

  end process;

  cpu_0_jtag_debug_module_begintransfer <= cpu_0_jtag_debug_module_begins_xfer;
  --~cpu_0_jtag_debug_module_reset assignment, which is an e_assign
  cpu_0_jtag_debug_module_reset <= NOT reset_n;
  --assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  cpu_0_jtag_debug_module_resetrequest_from_sa <= cpu_0_jtag_debug_module_resetrequest;
  cpu_0_jtag_debug_module_chipselect <= internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module OR internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
  --cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  cpu_0_jtag_debug_module_firsttransfer <= NOT ((cpu_0_jtag_debug_module_slavearbiterlockenable AND cpu_0_jtag_debug_module_any_continuerequest));
  --cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  cpu_0_jtag_debug_module_beginbursttransfer_internal <= cpu_0_jtag_debug_module_begins_xfer;
  --cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  cpu_0_jtag_debug_module_arbitration_holdoff_internal <= cpu_0_jtag_debug_module_begins_xfer AND cpu_0_jtag_debug_module_firsttransfer;
  --cpu_0_jtag_debug_module_write assignment, which is an e_mux
  cpu_0_jtag_debug_module_write <= internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module AND cpu_0_data_master_write;
  shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --cpu_0_jtag_debug_module_address mux, which is an e_mux
  cpu_0_jtag_debug_module_address <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module)) = '1'), (A_SRL(shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010"))), (A_SRL(shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master,std_logic_vector'("00000000000000000000000000000010")))), 9);
  shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master <= cpu_0_instruction_master_address_to_slave;
  --d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_cpu_0_jtag_debug_module_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
      end if;
    end if;

  end process;

  --cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  cpu_0_jtag_debug_module_waits_for_read <= cpu_0_jtag_debug_module_in_a_read_cycle AND cpu_0_jtag_debug_module_begins_xfer;
  --cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  cpu_0_jtag_debug_module_in_a_read_cycle <= ((internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module AND cpu_0_data_master_read)) OR ((internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module AND cpu_0_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= cpu_0_jtag_debug_module_in_a_read_cycle;
  --cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  cpu_0_jtag_debug_module_waits_for_write <= cpu_0_jtag_debug_module_in_a_write_cycle AND cpu_0_jtag_debug_module_begins_xfer;
  --cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  cpu_0_jtag_debug_module_in_a_write_cycle <= internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= cpu_0_jtag_debug_module_in_a_write_cycle;
  wait_for_cpu_0_jtag_debug_module_counter <= std_logic'('0');
  --cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  cpu_0_jtag_debug_module_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_cpu_0_jtag_debug_module <= internal_cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_granted_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_requests_cpu_0_jtag_debug_module <= internal_cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line16 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_0_data_master_granted_cpu_0_jtag_debug_module))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_0_instruction_master_granted_cpu_0_jtag_debug_module))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line16, now);
          write(write_line16, string'(": "));
          write(write_line16, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line16.all);
          deallocate (write_line16);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line17 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line17, now);
          write(write_line17, string'(": "));
          write(write_line17, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line17.all);
          deallocate (write_line17);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cpu_0_custom_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal endian_cpu_0_s1_result_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_custom_instruction_master_combo_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_custom_instruction_master_reset_n : OUT STD_LOGIC;
                 signal endian_cpu_0_s1_select : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_0_custom_instruction_master_arbitrator : entity is FALSE;
end entity cpu_0_custom_instruction_master_arbitrator;


architecture europa of cpu_0_custom_instruction_master_arbitrator is
                signal internal_endian_cpu_0_s1_select :  STD_LOGIC;

begin

  internal_endian_cpu_0_s1_select <= std_logic'('1');
  --cpu_0_custom_instruction_master_combo_result mux, which is an e_mux
  cpu_0_custom_instruction_master_combo_result <= A_REP(internal_endian_cpu_0_s1_select, 32) AND endian_cpu_0_s1_result_from_sa;
  --cpu_0_custom_instruction_master_reset_n local reset_n, which is an e_assign
  cpu_0_custom_instruction_master_reset_n <= reset_n;
  --vhdl renameroo for output signals
  endian_cpu_0_s1_select <= internal_endian_cpu_0_s1_select;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cpu_0_data_master_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_0_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_0_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal clock_1_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_1_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal clock_2_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_2_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal clock_3_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clock_3_in_waitrequest_from_sa : IN STD_LOGIC;
                 signal cpu_0_data_master_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_debugaccess : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_clock_0_in : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_clock_1_in : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_clock_2_in : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_clock_3_in : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_lcd_16207_0_control_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_granted_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_0_in : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_1_in : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_2_in : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_clock_3_in : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_lcd_16207_0_control_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_0_in : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_1_in : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_2_in : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_clock_3_in : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_0_in : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_1_in : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_2_in : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_clock_3_in : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_lcd_16207_0_control_slave : IN STD_LOGIC;
                 signal cpu_0_data_master_requests_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_clock_0_in_end_xfer : IN STD_LOGIC;
                 signal d1_clock_1_in_end_xfer : IN STD_LOGIC;
                 signal d1_clock_2_in_end_xfer : IN STD_LOGIC;
                 signal d1_clock_3_in_end_xfer : IN STD_LOGIC;
                 signal d1_cpu_0_jtag_debug_module_end_xfer : IN STD_LOGIC;
                 signal d1_dm9000a_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
                 signal d1_jtag_uart_0_avalon_jtag_slave_end_xfer : IN STD_LOGIC;
                 signal d1_lcd_16207_0_control_slave_end_xfer : IN STD_LOGIC;
                 signal d1_onchip_memory_0_s1_end_xfer : IN STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_irq_from_sa : IN STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal jtag_uart_0_avalon_jtag_slave_irq_from_sa : IN STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa : IN STD_LOGIC;
                 signal lcd_16207_0_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal lcd_16207_0_control_slave_wait_counter_eq_0 : IN STD_LOGIC;
                 signal lcd_16207_0_control_slave_wait_counter_eq_1 : IN STD_LOGIC;
                 signal onchip_memory_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_irq : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_data_master_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_0_data_master_arbitrator : entity is FALSE;
end entity cpu_0_data_master_arbitrator;


architecture europa of cpu_0_data_master_arbitrator is
                signal cpu_0_data_master_run :  STD_LOGIC;
                signal internal_cpu_0_data_master_address_to_slave :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal internal_cpu_0_data_master_waitrequest :  STD_LOGIC;
                signal p1_registered_cpu_0_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal r_0 :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;
                signal registered_cpu_0_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --r_0 master_run cascaded wait assignment, which is an e_assign
  r_0 <= Vector_To_Std_Logic((((((((((((((((((((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_clock_0_in OR NOT cpu_0_data_master_requests_clock_0_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_0_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_0_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_0_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_0_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_clock_1_in OR NOT cpu_0_data_master_requests_clock_1_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_1_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_1_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_1_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_1_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_clock_2_in OR NOT cpu_0_data_master_requests_clock_2_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_2_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_2_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_2_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_2_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_clock_3_in OR NOT cpu_0_data_master_requests_clock_3_in)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_3_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_3_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_clock_3_in OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT clock_3_in_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module OR NOT cpu_0_data_master_requests_cpu_0_jtag_debug_module)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_granted_cpu_0_jtag_debug_module OR NOT cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))));
  --cascaded wait assignment, which is an e_assign
  cpu_0_data_master_run <= r_0 AND r_1;
  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic(((((((((((((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave OR NOT cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_lcd_16207_0_control_slave OR NOT cpu_0_data_master_read)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(lcd_16207_0_control_slave_wait_counter_eq_1)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_lcd_16207_0_control_slave OR NOT cpu_0_data_master_write)))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(lcd_16207_0_control_slave_wait_counter_eq_1)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_data_master_write)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((cpu_0_data_master_qualified_request_onchip_memory_0_s1 OR registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1) OR NOT cpu_0_data_master_requests_onchip_memory_0_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_granted_onchip_memory_0_s1 OR NOT cpu_0_data_master_qualified_request_onchip_memory_0_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((((NOT cpu_0_data_master_qualified_request_onchip_memory_0_s1 OR NOT cpu_0_data_master_read) OR ((registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 AND cpu_0_data_master_read)))))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_data_master_qualified_request_onchip_memory_0_s1 OR NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_read OR cpu_0_data_master_write)))))))))));
  --optimize select-logic by passing only those address bits which matter.
  internal_cpu_0_data_master_address_to_slave <= Std_Logic_Vector'(A_ToStdLogicVector(cpu_0_data_master_address(17)) & std_logic_vector'("00") & cpu_0_data_master_address(14 DOWNTO 0));
  --unpredictable registered wait state incoming data, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      registered_cpu_0_data_master_readdata <= std_logic_vector'("00000000000000000000000000000000");
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
      end if;
    end if;

  end process;

  --registered readdata mux, which is an e_mux
  p1_registered_cpu_0_data_master_readdata <= (((((A_REP(NOT cpu_0_data_master_requests_clock_0_in, 32) OR (std_logic_vector'("000000000000000000000000") & (clock_0_in_readdata_from_sa)))) AND ((A_REP(NOT cpu_0_data_master_requests_clock_1_in, 32) OR (std_logic_vector'("000000000000000000000000") & (clock_1_in_readdata_from_sa))))) AND ((A_REP(NOT cpu_0_data_master_requests_clock_2_in, 32) OR (std_logic_vector'("000000000000000000000000") & (clock_2_in_readdata_from_sa))))) AND ((A_REP(NOT cpu_0_data_master_requests_clock_3_in, 32) OR (std_logic_vector'("000000000000000000000000") & (clock_3_in_readdata_from_sa))))) AND ((A_REP(NOT cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, 32) OR jtag_uart_0_avalon_jtag_slave_readdata_from_sa));
  --cpu_0/data_master readdata mux, which is an e_mux
  cpu_0_data_master_readdata <= (((((((((A_REP(NOT cpu_0_data_master_requests_clock_0_in, 32) OR registered_cpu_0_data_master_readdata)) AND ((A_REP(NOT cpu_0_data_master_requests_clock_1_in, 32) OR registered_cpu_0_data_master_readdata))) AND ((A_REP(NOT cpu_0_data_master_requests_clock_2_in, 32) OR registered_cpu_0_data_master_readdata))) AND ((A_REP(NOT cpu_0_data_master_requests_clock_3_in, 32) OR registered_cpu_0_data_master_readdata))) AND ((A_REP(NOT cpu_0_data_master_requests_cpu_0_jtag_debug_module, 32) OR cpu_0_jtag_debug_module_readdata_from_sa))) AND ((A_REP(NOT cpu_0_data_master_requests_dm9000a_0_avalon_slave_0, 32) OR (std_logic_vector'("0000000000000000") & (dm9000a_0_avalon_slave_0_readdata_from_sa))))) AND ((A_REP(NOT cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave, 32) OR registered_cpu_0_data_master_readdata))) AND ((A_REP(NOT cpu_0_data_master_requests_lcd_16207_0_control_slave, 32) OR (std_logic_vector'("000000000000000000000000") & (lcd_16207_0_control_slave_readdata_from_sa))))) AND ((A_REP(NOT cpu_0_data_master_requests_onchip_memory_0_s1, 32) OR onchip_memory_0_s1_readdata_from_sa));
  --actual waitrequest port, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_cpu_0_data_master_waitrequest <= Vector_To_Std_Logic(NOT std_logic_vector'("00000000000000000000000000000000"));
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        internal_cpu_0_data_master_waitrequest <= Vector_To_Std_Logic(NOT (A_WE_StdLogicVector((std_logic'((NOT ((cpu_0_data_master_read OR cpu_0_data_master_write)))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_data_master_run AND internal_cpu_0_data_master_waitrequest))))))));
      end if;
    end if;

  end process;

  --irq assign, which is an e_assign
  cpu_0_data_master_irq <= Std_Logic_Vector'(A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(dm9000a_0_avalon_slave_0_irq_from_sa) & A_ToStdLogicVector(jtag_uart_0_avalon_jtag_slave_irq_from_sa));
  --vhdl renameroo for output signals
  cpu_0_data_master_address_to_slave <= internal_cpu_0_data_master_address_to_slave;
  --vhdl renameroo for output signals
  cpu_0_data_master_waitrequest <= internal_cpu_0_data_master_waitrequest;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity cpu_0_instruction_master_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_instruction_master_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_instruction_master_granted_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_instruction_master_granted_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_instruction_master_read : IN STD_LOGIC;
                 signal cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_instruction_master_requests_cpu_0_jtag_debug_module : IN STD_LOGIC;
                 signal cpu_0_instruction_master_requests_onchip_memory_0_s1 : IN STD_LOGIC;
                 signal cpu_0_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal d1_cpu_0_jtag_debug_module_end_xfer : IN STD_LOGIC;
                 signal d1_onchip_memory_0_s1_end_xfer : IN STD_LOGIC;
                 signal onchip_memory_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_instruction_master_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_instruction_master_latency_counter : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_instruction_master_readdatavalid : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_waitrequest : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of cpu_0_instruction_master_arbitrator : entity is FALSE;
end entity cpu_0_instruction_master_arbitrator;


architecture europa of cpu_0_instruction_master_arbitrator is
                signal active_and_waiting_last_time :  STD_LOGIC;
                signal cpu_0_instruction_master_address_last_time :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal cpu_0_instruction_master_is_granted_some_slave :  STD_LOGIC;
                signal cpu_0_instruction_master_read_but_no_slave_selected :  STD_LOGIC;
                signal cpu_0_instruction_master_read_last_time :  STD_LOGIC;
                signal cpu_0_instruction_master_run :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_address_to_slave :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal internal_cpu_0_instruction_master_latency_counter :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_waitrequest :  STD_LOGIC;
                signal latency_load_value :  STD_LOGIC;
                signal p1_cpu_0_instruction_master_latency_counter :  STD_LOGIC;
                signal pre_flush_cpu_0_instruction_master_readdatavalid :  STD_LOGIC;
                signal r_0 :  STD_LOGIC;
                signal r_1 :  STD_LOGIC;

begin

  --r_0 master_run cascaded wait assignment, which is an e_assign
  r_0 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module OR NOT cpu_0_instruction_master_requests_cpu_0_jtag_debug_module)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_instruction_master_granted_cpu_0_jtag_debug_module OR NOT cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module)))))));
  --cascaded wait assignment, which is an e_assign
  cpu_0_instruction_master_run <= r_0 AND r_1;
  --r_1 master_run cascaded wait assignment, which is an e_assign
  r_1 <= Vector_To_Std_Logic((((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module OR NOT (cpu_0_instruction_master_read))))) OR (((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT d1_cpu_0_jtag_debug_module_end_xfer)))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((cpu_0_instruction_master_read)))))))) AND std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 OR NOT cpu_0_instruction_master_requests_onchip_memory_0_s1)))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((cpu_0_instruction_master_granted_onchip_memory_0_s1 OR NOT cpu_0_instruction_master_qualified_request_onchip_memory_0_s1)))))) AND (((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR((NOT cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 OR NOT cpu_0_instruction_master_read)))) OR ((std_logic_vector'("00000000000000000000000000000001") AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_read)))))))));
  --optimize select-logic by passing only those address bits which matter.
  internal_cpu_0_instruction_master_address_to_slave <= Std_Logic_Vector'(A_ToStdLogicVector(cpu_0_instruction_master_address(17)) & std_logic_vector'("00") & cpu_0_instruction_master_address(14 DOWNTO 0));
  --cpu_0_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_instruction_master_read_but_no_slave_selected <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        cpu_0_instruction_master_read_but_no_slave_selected <= (cpu_0_instruction_master_read AND cpu_0_instruction_master_run) AND NOT cpu_0_instruction_master_is_granted_some_slave;
      end if;
    end if;

  end process;

  --some slave is getting selected, which is an e_mux
  cpu_0_instruction_master_is_granted_some_slave <= cpu_0_instruction_master_granted_cpu_0_jtag_debug_module OR cpu_0_instruction_master_granted_onchip_memory_0_s1;
  --latent slave read data valids which may be flushed, which is an e_mux
  pre_flush_cpu_0_instruction_master_readdatavalid <= cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1;
  --latent slave read data valid which is not flushed, which is an e_mux
  cpu_0_instruction_master_readdatavalid <= (((cpu_0_instruction_master_read_but_no_slave_selected OR pre_flush_cpu_0_instruction_master_readdatavalid) OR cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module) OR cpu_0_instruction_master_read_but_no_slave_selected) OR pre_flush_cpu_0_instruction_master_readdatavalid;
  --cpu_0/instruction_master readdata mux, which is an e_mux
  cpu_0_instruction_master_readdata <= ((A_REP(NOT ((cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module AND cpu_0_instruction_master_read)) , 32) OR cpu_0_jtag_debug_module_readdata_from_sa)) AND ((A_REP(NOT cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1, 32) OR onchip_memory_0_s1_readdata_from_sa));
  --actual waitrequest port, which is an e_assign
  internal_cpu_0_instruction_master_waitrequest <= NOT cpu_0_instruction_master_run;
  --latent max counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_cpu_0_instruction_master_latency_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        internal_cpu_0_instruction_master_latency_counter <= p1_cpu_0_instruction_master_latency_counter;
      end if;
    end if;

  end process;

  --latency counter load mux, which is an e_mux
  p1_cpu_0_instruction_master_latency_counter <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(((cpu_0_instruction_master_run AND cpu_0_instruction_master_read))) = '1'), (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(latency_load_value))), A_WE_StdLogicVector((std_logic'((internal_cpu_0_instruction_master_latency_counter)) = '1'), ((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(internal_cpu_0_instruction_master_latency_counter))) - std_logic_vector'("000000000000000000000000000000001")), std_logic_vector'("000000000000000000000000000000000"))));
  --read latency load values, which is an e_mux
  latency_load_value <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_requests_onchip_memory_0_s1))) AND std_logic_vector'("00000000000000000000000000000001")));
  --vhdl renameroo for output signals
  cpu_0_instruction_master_address_to_slave <= internal_cpu_0_instruction_master_address_to_slave;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_latency_counter <= internal_cpu_0_instruction_master_latency_counter;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_waitrequest <= internal_cpu_0_instruction_master_waitrequest;
--synthesis translate_off
    --cpu_0_instruction_master_address check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        cpu_0_instruction_master_address_last_time <= std_logic_vector'("000000000000000000");
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
        end if;
      end if;

    end process;

    --cpu_0/instruction_master waited last time, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        active_and_waiting_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          active_and_waiting_last_time <= internal_cpu_0_instruction_master_waitrequest AND (cpu_0_instruction_master_read);
        end if;
      end if;

    end process;

    --cpu_0_instruction_master_address matches last port_name, which is an e_process
    process (active_and_waiting_last_time, cpu_0_instruction_master_address, cpu_0_instruction_master_address_last_time)
    VARIABLE write_line18 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((cpu_0_instruction_master_address /= cpu_0_instruction_master_address_last_time))))) = '1' then 
          write(write_line18, now);
          write(write_line18, string'(": "));
          write(write_line18, string'("cpu_0_instruction_master_address did not heed wait!!!"));
          write(output, write_line18.all);
          deallocate (write_line18);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

    --cpu_0_instruction_master_read check against wait, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        cpu_0_instruction_master_read_last_time <= std_logic'('0');
      elsif clk'event and clk = '1' then
        if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
          cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
        end if;
      end if;

    end process;

    --cpu_0_instruction_master_read matches last port_name, which is an e_process
    process (active_and_waiting_last_time, cpu_0_instruction_master_read, cpu_0_instruction_master_read_last_time)
    VARIABLE write_line19 : line;
    begin
        if std_logic'((active_and_waiting_last_time AND to_std_logic(((std_logic'(cpu_0_instruction_master_read) /= std_logic'(cpu_0_instruction_master_read_last_time)))))) = '1' then 
          write(write_line19, now);
          write(write_line19, string'(": "));
          write(write_line19, string'("cpu_0_instruction_master_read did not heed wait!!!"));
          write(output, write_line19.all);
          deallocate (write_line19);
          assert false report "VHDL STOP" severity failure;
        end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dm9000a_0_avalon_slave_0_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal dm9000a_0_avalon_slave_0_irq : IN STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                 signal d1_dm9000a_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_address : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_chipselect_n : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_irq_from_sa : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_read_n : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal dm9000a_0_avalon_slave_0_reset_n : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_write_n : OUT STD_LOGIC;
                 signal dm9000a_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of dm9000a_0_avalon_slave_0_arbitrator : entity is FALSE;
end entity dm9000a_0_avalon_slave_0_arbitrator;


architecture europa of dm9000a_0_avalon_slave_0_arbitrator is
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_allgrants :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_allow_new_arb_cycle :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_any_bursting_master_saved_grant :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_any_continuerequest :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_arb_counter_enable :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_arb_share_counter :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_arb_share_counter_next_value :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_arb_share_set_values :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_beginbursttransfer_internal :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_begins_xfer :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_end_xfer :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_firsttransfer :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_grant_vector :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_in_a_read_cycle :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_in_a_write_cycle :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_master_qreq_vector :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_non_bursting_master_requests :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_slavearbiterlockenable :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_slavearbiterlockenable2 :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_waits_for_read :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_waits_for_write :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal shifted_address_to_dm9000a_0_avalon_slave_0_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_dm9000a_0_avalon_slave_0_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT dm9000a_0_avalon_slave_0_end_xfer;
      end if;
    end if;

  end process;

  dm9000a_0_avalon_slave_0_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0);
  --assign dm9000a_0_avalon_slave_0_readdata_from_sa = dm9000a_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  dm9000a_0_avalon_slave_0_readdata_from_sa <= dm9000a_0_avalon_slave_0_readdata;
  internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100000100001011000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --dm9000a_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
  dm9000a_0_avalon_slave_0_arb_share_set_values <= std_logic'('1');
  --dm9000a_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
  dm9000a_0_avalon_slave_0_non_bursting_master_requests <= internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0;
  --dm9000a_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
  dm9000a_0_avalon_slave_0_any_bursting_master_saved_grant <= std_logic'('0');
  --dm9000a_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
  dm9000a_0_avalon_slave_0_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(dm9000a_0_avalon_slave_0_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dm9000a_0_avalon_slave_0_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(dm9000a_0_avalon_slave_0_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(dm9000a_0_avalon_slave_0_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --dm9000a_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
  dm9000a_0_avalon_slave_0_allgrants <= dm9000a_0_avalon_slave_0_grant_vector;
  --dm9000a_0_avalon_slave_0_end_xfer assignment, which is an e_assign
  dm9000a_0_avalon_slave_0_end_xfer <= NOT ((dm9000a_0_avalon_slave_0_waits_for_read OR dm9000a_0_avalon_slave_0_waits_for_write));
  --end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 <= dm9000a_0_avalon_slave_0_end_xfer AND (((NOT dm9000a_0_avalon_slave_0_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --dm9000a_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
  dm9000a_0_avalon_slave_0_arb_counter_enable <= ((end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 AND dm9000a_0_avalon_slave_0_allgrants)) OR ((end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 AND NOT dm9000a_0_avalon_slave_0_non_bursting_master_requests));
  --dm9000a_0_avalon_slave_0_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dm9000a_0_avalon_slave_0_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(dm9000a_0_avalon_slave_0_arb_counter_enable) = '1' then 
        dm9000a_0_avalon_slave_0_arb_share_counter <= dm9000a_0_avalon_slave_0_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --dm9000a_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dm9000a_0_avalon_slave_0_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((dm9000a_0_avalon_slave_0_master_qreq_vector AND end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0)) OR ((end_xfer_arb_share_counter_term_dm9000a_0_avalon_slave_0 AND NOT dm9000a_0_avalon_slave_0_non_bursting_master_requests)))) = '1' then 
        dm9000a_0_avalon_slave_0_slavearbiterlockenable <= dm9000a_0_avalon_slave_0_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master dm9000a_0/avalon_slave_0 arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= dm9000a_0_avalon_slave_0_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --dm9000a_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  dm9000a_0_avalon_slave_0_slavearbiterlockenable2 <= dm9000a_0_avalon_slave_0_arb_share_counter_next_value;
  --cpu_0/data_master dm9000a_0/avalon_slave_0 arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= dm9000a_0_avalon_slave_0_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --dm9000a_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
  dm9000a_0_avalon_slave_0_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0;
  --dm9000a_0_avalon_slave_0_writedata mux, which is an e_mux
  dm9000a_0_avalon_slave_0_writedata <= cpu_0_data_master_writedata (15 DOWNTO 0);
  --master is always granted when requested
  internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0;
  --cpu_0/data_master saved-grant dm9000a_0/avalon_slave_0, which is an e_assign
  cpu_0_data_master_saved_grant_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0;
  --allow new arb cycle for dm9000a_0/avalon_slave_0, which is an e_assign
  dm9000a_0_avalon_slave_0_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  dm9000a_0_avalon_slave_0_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  dm9000a_0_avalon_slave_0_master_qreq_vector <= std_logic'('1');
  --dm9000a_0_avalon_slave_0_reset_n assignment, which is an e_assign
  dm9000a_0_avalon_slave_0_reset_n <= reset_n;
  dm9000a_0_avalon_slave_0_chipselect_n <= NOT internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0;
  --dm9000a_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
  dm9000a_0_avalon_slave_0_firsttransfer <= NOT ((dm9000a_0_avalon_slave_0_slavearbiterlockenable AND dm9000a_0_avalon_slave_0_any_continuerequest));
  --dm9000a_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
  dm9000a_0_avalon_slave_0_beginbursttransfer_internal <= dm9000a_0_avalon_slave_0_begins_xfer;
  --~dm9000a_0_avalon_slave_0_read_n assignment, which is an e_mux
  dm9000a_0_avalon_slave_0_read_n <= NOT ((internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 AND cpu_0_data_master_read));
  --~dm9000a_0_avalon_slave_0_write_n assignment, which is an e_mux
  dm9000a_0_avalon_slave_0_write_n <= NOT ((internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 AND cpu_0_data_master_write));
  shifted_address_to_dm9000a_0_avalon_slave_0_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --dm9000a_0_avalon_slave_0_address mux, which is an e_mux
  dm9000a_0_avalon_slave_0_address <= Vector_To_Std_Logic(A_SRL(shifted_address_to_dm9000a_0_avalon_slave_0_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")));
  --d1_dm9000a_0_avalon_slave_0_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_dm9000a_0_avalon_slave_0_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_dm9000a_0_avalon_slave_0_end_xfer <= dm9000a_0_avalon_slave_0_end_xfer;
      end if;
    end if;

  end process;

  --dm9000a_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
  dm9000a_0_avalon_slave_0_waits_for_read <= dm9000a_0_avalon_slave_0_in_a_read_cycle AND dm9000a_0_avalon_slave_0_begins_xfer;
  --dm9000a_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
  dm9000a_0_avalon_slave_0_in_a_read_cycle <= internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= dm9000a_0_avalon_slave_0_in_a_read_cycle;
  --dm9000a_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
  dm9000a_0_avalon_slave_0_waits_for_write <= dm9000a_0_avalon_slave_0_in_a_write_cycle AND dm9000a_0_avalon_slave_0_begins_xfer;
  --dm9000a_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
  dm9000a_0_avalon_slave_0_in_a_write_cycle <= internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= dm9000a_0_avalon_slave_0_in_a_write_cycle;
  wait_for_dm9000a_0_avalon_slave_0_counter <= std_logic'('0');
  --assign dm9000a_0_avalon_slave_0_irq_from_sa = dm9000a_0_avalon_slave_0_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  dm9000a_0_avalon_slave_0_irq_from_sa <= dm9000a_0_avalon_slave_0_irq;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_granted_dm9000a_0_avalon_slave_0;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 <= internal_cpu_0_data_master_requests_dm9000a_0_avalon_slave_0;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity endian_cpu_0_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_custom_instruction_master_combo_dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_custom_instruction_master_combo_datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal endian_cpu_0_s1_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal endian_cpu_0_s1_select : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal endian_cpu_0_s1_dataa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal endian_cpu_0_s1_datab : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal endian_cpu_0_s1_result_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of endian_cpu_0_s1_arbitrator : entity is FALSE;
end entity endian_cpu_0_s1_arbitrator;


architecture europa of endian_cpu_0_s1_arbitrator is

begin

  endian_cpu_0_s1_dataa <= cpu_0_custom_instruction_master_combo_dataa;
  endian_cpu_0_s1_datab <= cpu_0_custom_instruction_master_combo_datab;
  --assign endian_cpu_0_s1_result_from_sa = endian_cpu_0_s1_result so that symbol knows where to group signals which may go to master only, which is an e_assign
  endian_cpu_0_s1_result_from_sa <= endian_cpu_0_s1_result;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity jtag_uart_0_avalon_jtag_slave_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal jtag_uart_0_avalon_jtag_slave_dataavailable : IN STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_irq : IN STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal jtag_uart_0_avalon_jtag_slave_readyfordata : IN STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_waitrequest : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                 signal d1_jtag_uart_0_avalon_jtag_slave_end_xfer : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_address : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_chipselect : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_irq_from_sa : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_read_n : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_reset_n : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_write_n : OUT STD_LOGIC;
                 signal jtag_uart_0_avalon_jtag_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of jtag_uart_0_avalon_jtag_slave_arbitrator : entity is FALSE;
end entity jtag_uart_0_avalon_jtag_slave_arbitrator;


architecture europa of jtag_uart_0_avalon_jtag_slave_arbitrator is
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal internal_jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_allgrants :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_any_continuerequest :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_arb_counter_enable :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_arb_share_counter :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_arb_share_set_values :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_begins_xfer :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_end_xfer :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_firsttransfer :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_grant_vector :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_in_a_read_cycle :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_in_a_write_cycle :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_master_qreq_vector :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_waits_for_read :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_waits_for_write :  STD_LOGIC;
                signal shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_jtag_uart_0_avalon_jtag_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT jtag_uart_0_avalon_jtag_slave_end_xfer;
      end if;
    end if;

  end process;

  jtag_uart_0_avalon_jtag_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave);
  --assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_readdata_from_sa <= jtag_uart_0_avalon_jtag_slave_readdata;
  internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 3) & std_logic_vector'("000")) = std_logic_vector'("100000100001010000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa <= jtag_uart_0_avalon_jtag_slave_dataavailable;
  --assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa <= jtag_uart_0_avalon_jtag_slave_readyfordata;
  --assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  internal_jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa <= jtag_uart_0_avalon_jtag_slave_waitrequest;
  --jtag_uart_0_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_arb_share_set_values <= std_logic'('1');
  --jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests <= internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
  --jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant <= std_logic'('0');
  --jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(jtag_uart_0_avalon_jtag_slave_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(jtag_uart_0_avalon_jtag_slave_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(jtag_uart_0_avalon_jtag_slave_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(jtag_uart_0_avalon_jtag_slave_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --jtag_uart_0_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_allgrants <= jtag_uart_0_avalon_jtag_slave_grant_vector;
  --jtag_uart_0_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_end_xfer <= NOT ((jtag_uart_0_avalon_jtag_slave_waits_for_read OR jtag_uart_0_avalon_jtag_slave_waits_for_write));
  --end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave <= jtag_uart_0_avalon_jtag_slave_end_xfer AND (((NOT jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --jtag_uart_0_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_arb_counter_enable <= ((end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave AND jtag_uart_0_avalon_jtag_slave_allgrants)) OR ((end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave AND NOT jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests));
  --jtag_uart_0_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      jtag_uart_0_avalon_jtag_slave_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(jtag_uart_0_avalon_jtag_slave_arb_counter_enable) = '1' then 
        jtag_uart_0_avalon_jtag_slave_arb_share_counter <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((jtag_uart_0_avalon_jtag_slave_master_qreq_vector AND end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave)) OR ((end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave AND NOT jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests)))) = '1' then 
        jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
  --cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --jtag_uart_0_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave AND NOT ((((cpu_0_data_master_read AND (NOT cpu_0_data_master_waitrequest))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))));
  --jtag_uart_0_avalon_jtag_slave_writedata mux, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_writedata <= cpu_0_data_master_writedata;
  --master is always granted when requested
  internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
  --cpu_0/data_master saved-grant jtag_uart_0/avalon_jtag_slave, which is an e_assign
  cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
  --allow new arb cycle for jtag_uart_0/avalon_jtag_slave, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  jtag_uart_0_avalon_jtag_slave_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  jtag_uart_0_avalon_jtag_slave_master_qreq_vector <= std_logic'('1');
  --jtag_uart_0_avalon_jtag_slave_reset_n assignment, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_reset_n <= reset_n;
  jtag_uart_0_avalon_jtag_slave_chipselect <= internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
  --jtag_uart_0_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_firsttransfer <= NOT ((jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable AND jtag_uart_0_avalon_jtag_slave_any_continuerequest));
  --jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal <= jtag_uart_0_avalon_jtag_slave_begins_xfer;
  --~jtag_uart_0_avalon_jtag_slave_read_n assignment, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_read_n <= NOT ((internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave AND cpu_0_data_master_read));
  --~jtag_uart_0_avalon_jtag_slave_write_n assignment, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_write_n <= NOT ((internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave AND cpu_0_data_master_write));
  shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --jtag_uart_0_avalon_jtag_slave_address mux, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_address <= Vector_To_Std_Logic(A_SRL(shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")));
  --d1_jtag_uart_0_avalon_jtag_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= jtag_uart_0_avalon_jtag_slave_end_xfer;
      end if;
    end if;

  end process;

  --jtag_uart_0_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_waits_for_read <= jtag_uart_0_avalon_jtag_slave_in_a_read_cycle AND internal_jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  --jtag_uart_0_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_in_a_read_cycle <= internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
  --jtag_uart_0_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  jtag_uart_0_avalon_jtag_slave_waits_for_write <= jtag_uart_0_avalon_jtag_slave_in_a_write_cycle AND internal_jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
  --jtag_uart_0_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_in_a_write_cycle <= internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
  wait_for_jtag_uart_0_avalon_jtag_slave_counter <= std_logic'('0');
  --assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  jtag_uart_0_avalon_jtag_slave_irq_from_sa <= jtag_uart_0_avalon_jtag_slave_irq;
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave <= internal_cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
  --vhdl renameroo for output signals
  jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa <= internal_jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity lcd_16207_0_control_slave_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal lcd_16207_0_control_slave_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_granted_lcd_16207_0_control_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_lcd_16207_0_control_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_lcd_16207_0_control_slave : OUT STD_LOGIC;
                 signal d1_lcd_16207_0_control_slave_end_xfer : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal lcd_16207_0_control_slave_begintransfer : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_read : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal lcd_16207_0_control_slave_wait_counter_eq_0 : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_wait_counter_eq_1 : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_write : OUT STD_LOGIC;
                 signal lcd_16207_0_control_slave_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of lcd_16207_0_control_slave_arbitrator : entity is FALSE;
end entity lcd_16207_0_control_slave_arbitrator;


architecture europa of lcd_16207_0_control_slave_arbitrator is
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_lcd_16207_0_control_slave :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_lcd_16207_0_control_slave :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_lcd_16207_0_control_slave :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_lcd_16207_0_control_slave :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_lcd_16207_0_control_slave :  STD_LOGIC;
                signal internal_lcd_16207_0_control_slave_wait_counter_eq_0 :  STD_LOGIC;
                signal lcd_16207_0_control_slave_allgrants :  STD_LOGIC;
                signal lcd_16207_0_control_slave_allow_new_arb_cycle :  STD_LOGIC;
                signal lcd_16207_0_control_slave_any_bursting_master_saved_grant :  STD_LOGIC;
                signal lcd_16207_0_control_slave_any_continuerequest :  STD_LOGIC;
                signal lcd_16207_0_control_slave_arb_counter_enable :  STD_LOGIC;
                signal lcd_16207_0_control_slave_arb_share_counter :  STD_LOGIC;
                signal lcd_16207_0_control_slave_arb_share_counter_next_value :  STD_LOGIC;
                signal lcd_16207_0_control_slave_arb_share_set_values :  STD_LOGIC;
                signal lcd_16207_0_control_slave_beginbursttransfer_internal :  STD_LOGIC;
                signal lcd_16207_0_control_slave_begins_xfer :  STD_LOGIC;
                signal lcd_16207_0_control_slave_counter_load_value :  STD_LOGIC_VECTOR (5 DOWNTO 0);
                signal lcd_16207_0_control_slave_end_xfer :  STD_LOGIC;
                signal lcd_16207_0_control_slave_firsttransfer :  STD_LOGIC;
                signal lcd_16207_0_control_slave_grant_vector :  STD_LOGIC;
                signal lcd_16207_0_control_slave_in_a_read_cycle :  STD_LOGIC;
                signal lcd_16207_0_control_slave_in_a_write_cycle :  STD_LOGIC;
                signal lcd_16207_0_control_slave_master_qreq_vector :  STD_LOGIC;
                signal lcd_16207_0_control_slave_non_bursting_master_requests :  STD_LOGIC;
                signal lcd_16207_0_control_slave_pretend_byte_enable :  STD_LOGIC;
                signal lcd_16207_0_control_slave_slavearbiterlockenable :  STD_LOGIC;
                signal lcd_16207_0_control_slave_slavearbiterlockenable2 :  STD_LOGIC;
                signal lcd_16207_0_control_slave_wait_counter :  STD_LOGIC_VECTOR (5 DOWNTO 0);
                signal lcd_16207_0_control_slave_waits_for_read :  STD_LOGIC;
                signal lcd_16207_0_control_slave_waits_for_write :  STD_LOGIC;
                signal shifted_address_to_lcd_16207_0_control_slave_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_lcd_16207_0_control_slave_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT lcd_16207_0_control_slave_end_xfer;
      end if;
    end if;

  end process;

  lcd_16207_0_control_slave_begins_xfer <= NOT d1_reasons_to_wait AND (internal_cpu_0_data_master_qualified_request_lcd_16207_0_control_slave);
  --assign lcd_16207_0_control_slave_readdata_from_sa = lcd_16207_0_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  lcd_16207_0_control_slave_readdata_from_sa <= lcd_16207_0_control_slave_readdata;
  internal_cpu_0_data_master_requests_lcd_16207_0_control_slave <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 4) & std_logic_vector'("0000")) = std_logic_vector'("100000100000000000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --lcd_16207_0_control_slave_arb_share_counter set values, which is an e_mux
  lcd_16207_0_control_slave_arb_share_set_values <= std_logic'('1');
  --lcd_16207_0_control_slave_non_bursting_master_requests mux, which is an e_mux
  lcd_16207_0_control_slave_non_bursting_master_requests <= internal_cpu_0_data_master_requests_lcd_16207_0_control_slave;
  --lcd_16207_0_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
  lcd_16207_0_control_slave_any_bursting_master_saved_grant <= std_logic'('0');
  --lcd_16207_0_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  lcd_16207_0_control_slave_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(lcd_16207_0_control_slave_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(lcd_16207_0_control_slave_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(lcd_16207_0_control_slave_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(lcd_16207_0_control_slave_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --lcd_16207_0_control_slave_allgrants all slave grants, which is an e_mux
  lcd_16207_0_control_slave_allgrants <= lcd_16207_0_control_slave_grant_vector;
  --lcd_16207_0_control_slave_end_xfer assignment, which is an e_assign
  lcd_16207_0_control_slave_end_xfer <= NOT ((lcd_16207_0_control_slave_waits_for_read OR lcd_16207_0_control_slave_waits_for_write));
  --end_xfer_arb_share_counter_term_lcd_16207_0_control_slave arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_lcd_16207_0_control_slave <= lcd_16207_0_control_slave_end_xfer AND (((NOT lcd_16207_0_control_slave_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --lcd_16207_0_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  lcd_16207_0_control_slave_arb_counter_enable <= ((end_xfer_arb_share_counter_term_lcd_16207_0_control_slave AND lcd_16207_0_control_slave_allgrants)) OR ((end_xfer_arb_share_counter_term_lcd_16207_0_control_slave AND NOT lcd_16207_0_control_slave_non_bursting_master_requests));
  --lcd_16207_0_control_slave_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      lcd_16207_0_control_slave_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(lcd_16207_0_control_slave_arb_counter_enable) = '1' then 
        lcd_16207_0_control_slave_arb_share_counter <= lcd_16207_0_control_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --lcd_16207_0_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      lcd_16207_0_control_slave_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((lcd_16207_0_control_slave_master_qreq_vector AND end_xfer_arb_share_counter_term_lcd_16207_0_control_slave)) OR ((end_xfer_arb_share_counter_term_lcd_16207_0_control_slave AND NOT lcd_16207_0_control_slave_non_bursting_master_requests)))) = '1' then 
        lcd_16207_0_control_slave_slavearbiterlockenable <= lcd_16207_0_control_slave_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master lcd_16207_0/control_slave arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= lcd_16207_0_control_slave_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --lcd_16207_0_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  lcd_16207_0_control_slave_slavearbiterlockenable2 <= lcd_16207_0_control_slave_arb_share_counter_next_value;
  --cpu_0/data_master lcd_16207_0/control_slave arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= lcd_16207_0_control_slave_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --lcd_16207_0_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  lcd_16207_0_control_slave_any_continuerequest <= std_logic'('1');
  --cpu_0_data_master_continuerequest continued request, which is an e_assign
  cpu_0_data_master_continuerequest <= std_logic'('1');
  internal_cpu_0_data_master_qualified_request_lcd_16207_0_control_slave <= internal_cpu_0_data_master_requests_lcd_16207_0_control_slave;
  --lcd_16207_0_control_slave_writedata mux, which is an e_mux
  lcd_16207_0_control_slave_writedata <= cpu_0_data_master_writedata (7 DOWNTO 0);
  --master is always granted when requested
  internal_cpu_0_data_master_granted_lcd_16207_0_control_slave <= internal_cpu_0_data_master_qualified_request_lcd_16207_0_control_slave;
  --cpu_0/data_master saved-grant lcd_16207_0/control_slave, which is an e_assign
  cpu_0_data_master_saved_grant_lcd_16207_0_control_slave <= internal_cpu_0_data_master_requests_lcd_16207_0_control_slave;
  --allow new arb cycle for lcd_16207_0/control_slave, which is an e_assign
  lcd_16207_0_control_slave_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  lcd_16207_0_control_slave_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  lcd_16207_0_control_slave_master_qreq_vector <= std_logic'('1');
  lcd_16207_0_control_slave_begintransfer <= lcd_16207_0_control_slave_begins_xfer;
  --lcd_16207_0_control_slave_firsttransfer first transaction, which is an e_assign
  lcd_16207_0_control_slave_firsttransfer <= NOT ((lcd_16207_0_control_slave_slavearbiterlockenable AND lcd_16207_0_control_slave_any_continuerequest));
  --lcd_16207_0_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  lcd_16207_0_control_slave_beginbursttransfer_internal <= lcd_16207_0_control_slave_begins_xfer;
  --lcd_16207_0_control_slave_read assignment, which is an e_mux
  lcd_16207_0_control_slave_read <= (((internal_cpu_0_data_master_granted_lcd_16207_0_control_slave AND cpu_0_data_master_read)) AND NOT lcd_16207_0_control_slave_begins_xfer) AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter))<std_logic_vector'("00000000000000000000000000001101"))));
  --lcd_16207_0_control_slave_write assignment, which is an e_mux
  lcd_16207_0_control_slave_write <= (((((internal_cpu_0_data_master_granted_lcd_16207_0_control_slave AND cpu_0_data_master_write)) AND NOT lcd_16207_0_control_slave_begins_xfer) AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter))>=std_logic_vector'("00000000000000000000000000001101"))))) AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter))<std_logic_vector'("00000000000000000000000000011010"))))) AND lcd_16207_0_control_slave_pretend_byte_enable;
  shifted_address_to_lcd_16207_0_control_slave_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --lcd_16207_0_control_slave_address mux, which is an e_mux
  lcd_16207_0_control_slave_address <= A_EXT (A_SRL(shifted_address_to_lcd_16207_0_control_slave_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010")), 2);
  --d1_lcd_16207_0_control_slave_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_lcd_16207_0_control_slave_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_lcd_16207_0_control_slave_end_xfer <= lcd_16207_0_control_slave_end_xfer;
      end if;
    end if;

  end process;

  --lcd_16207_0_control_slave_wait_counter_eq_1 assignment, which is an e_assign
  lcd_16207_0_control_slave_wait_counter_eq_1 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter)) = std_logic_vector'("00000000000000000000000000000001")));
  --lcd_16207_0_control_slave_waits_for_read in a cycle, which is an e_mux
  lcd_16207_0_control_slave_waits_for_read <= lcd_16207_0_control_slave_in_a_read_cycle AND wait_for_lcd_16207_0_control_slave_counter;
  --lcd_16207_0_control_slave_in_a_read_cycle assignment, which is an e_assign
  lcd_16207_0_control_slave_in_a_read_cycle <= internal_cpu_0_data_master_granted_lcd_16207_0_control_slave AND cpu_0_data_master_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= lcd_16207_0_control_slave_in_a_read_cycle;
  --lcd_16207_0_control_slave_waits_for_write in a cycle, which is an e_mux
  lcd_16207_0_control_slave_waits_for_write <= lcd_16207_0_control_slave_in_a_write_cycle AND wait_for_lcd_16207_0_control_slave_counter;
  --lcd_16207_0_control_slave_in_a_write_cycle assignment, which is an e_assign
  lcd_16207_0_control_slave_in_a_write_cycle <= internal_cpu_0_data_master_granted_lcd_16207_0_control_slave AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= lcd_16207_0_control_slave_in_a_write_cycle;
  internal_lcd_16207_0_control_slave_wait_counter_eq_0 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter)) = std_logic_vector'("00000000000000000000000000000000")));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      lcd_16207_0_control_slave_wait_counter <= std_logic_vector'("000000");
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        lcd_16207_0_control_slave_wait_counter <= lcd_16207_0_control_slave_counter_load_value;
      end if;
    end if;

  end process;

  lcd_16207_0_control_slave_counter_load_value <= A_EXT (A_WE_StdLogicVector((std_logic'(((lcd_16207_0_control_slave_in_a_read_cycle AND lcd_16207_0_control_slave_begins_xfer))) = '1'), std_logic_vector'("000000000000000000000000000011000"), A_WE_StdLogicVector((std_logic'(((lcd_16207_0_control_slave_in_a_write_cycle AND lcd_16207_0_control_slave_begins_xfer))) = '1'), std_logic_vector'("000000000000000000000000000100101"), A_WE_StdLogicVector((std_logic'((NOT internal_lcd_16207_0_control_slave_wait_counter_eq_0)) = '1'), ((std_logic_vector'("000000000000000000000000000") & (lcd_16207_0_control_slave_wait_counter)) - std_logic_vector'("000000000000000000000000000000001")), std_logic_vector'("000000000000000000000000000000000")))), 6);
  wait_for_lcd_16207_0_control_slave_counter <= lcd_16207_0_control_slave_begins_xfer OR NOT internal_lcd_16207_0_control_slave_wait_counter_eq_0;
  --lcd_16207_0_control_slave_pretend_byte_enable byte enable port mux, which is an e_mux
  lcd_16207_0_control_slave_pretend_byte_enable <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_lcd_16207_0_control_slave)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))));
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_lcd_16207_0_control_slave <= internal_cpu_0_data_master_granted_lcd_16207_0_control_slave;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_lcd_16207_0_control_slave <= internal_cpu_0_data_master_qualified_request_lcd_16207_0_control_slave;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_lcd_16207_0_control_slave <= internal_cpu_0_data_master_requests_lcd_16207_0_control_slave;
  --vhdl renameroo for output signals
  lcd_16207_0_control_slave_wait_counter_eq_0 <= internal_lcd_16207_0_control_slave_wait_counter_eq_0;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity onchip_memory_0_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_0_data_master_read : IN STD_LOGIC;
                 signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_0_data_master_write : IN STD_LOGIC;
                 signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_0_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal cpu_0_instruction_master_latency_counter : IN STD_LOGIC;
                 signal cpu_0_instruction_master_read : IN STD_LOGIC;
                 signal onchip_memory_0_s1_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal cpu_0_data_master_granted_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_data_master_qualified_request_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_data_master_requests_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_granted_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal cpu_0_instruction_master_requests_onchip_memory_0_s1 : OUT STD_LOGIC;
                 signal d1_onchip_memory_0_s1_end_xfer : OUT STD_LOGIC;
                 signal onchip_memory_0_s1_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                 signal onchip_memory_0_s1_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal onchip_memory_0_s1_chipselect : OUT STD_LOGIC;
                 signal onchip_memory_0_s1_clken : OUT STD_LOGIC;
                 signal onchip_memory_0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal onchip_memory_0_s1_write : OUT STD_LOGIC;
                 signal onchip_memory_0_s1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of onchip_memory_0_s1_arbitrator : entity is FALSE;
end entity onchip_memory_0_s1_arbitrator;


architecture europa of onchip_memory_0_s1_arbitrator is
                signal cpu_0_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_data_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_data_master_continuerequest :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register_in :  STD_LOGIC;
                signal cpu_0_data_master_saved_grant_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_instruction_master_arbiterlock :  STD_LOGIC;
                signal cpu_0_instruction_master_arbiterlock2 :  STD_LOGIC;
                signal cpu_0_instruction_master_continuerequest :  STD_LOGIC;
                signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register :  STD_LOGIC;
                signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_in :  STD_LOGIC;
                signal cpu_0_instruction_master_saved_grant_onchip_memory_0_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_onchip_memory_0_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_0_data_master_granted_onchip_memory_0_s1 :  STD_LOGIC;
                signal internal_cpu_0_data_master_qualified_request_onchip_memory_0_s1 :  STD_LOGIC;
                signal internal_cpu_0_data_master_requests_onchip_memory_0_s1 :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_granted_onchip_memory_0_s1 :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 :  STD_LOGIC;
                signal internal_cpu_0_instruction_master_requests_onchip_memory_0_s1 :  STD_LOGIC;
                signal last_cycle_cpu_0_data_master_granted_slave_onchip_memory_0_s1 :  STD_LOGIC;
                signal last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory_0_s1 :  STD_LOGIC;
                signal onchip_memory_0_s1_allgrants :  STD_LOGIC;
                signal onchip_memory_0_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal onchip_memory_0_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal onchip_memory_0_s1_any_continuerequest :  STD_LOGIC;
                signal onchip_memory_0_s1_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_arb_counter_enable :  STD_LOGIC;
                signal onchip_memory_0_s1_arb_share_counter :  STD_LOGIC;
                signal onchip_memory_0_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal onchip_memory_0_s1_arb_share_set_values :  STD_LOGIC;
                signal onchip_memory_0_s1_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_arbitration_holdoff_internal :  STD_LOGIC;
                signal onchip_memory_0_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal onchip_memory_0_s1_begins_xfer :  STD_LOGIC;
                signal onchip_memory_0_s1_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal onchip_memory_0_s1_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_end_xfer :  STD_LOGIC;
                signal onchip_memory_0_s1_firsttransfer :  STD_LOGIC;
                signal onchip_memory_0_s1_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_in_a_read_cycle :  STD_LOGIC;
                signal onchip_memory_0_s1_in_a_write_cycle :  STD_LOGIC;
                signal onchip_memory_0_s1_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_non_bursting_master_requests :  STD_LOGIC;
                signal onchip_memory_0_s1_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal onchip_memory_0_s1_slavearbiterlockenable :  STD_LOGIC;
                signal onchip_memory_0_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal onchip_memory_0_s1_waits_for_read :  STD_LOGIC;
                signal onchip_memory_0_s1_waits_for_write :  STD_LOGIC;
                signal p1_cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register :  STD_LOGIC;
                signal p1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register :  STD_LOGIC;
                signal shifted_address_to_onchip_memory_0_s1_from_cpu_0_data_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal shifted_address_to_onchip_memory_0_s1_from_cpu_0_instruction_master :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal wait_for_onchip_memory_0_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT onchip_memory_0_s1_end_xfer;
      end if;
    end if;

  end process;

  onchip_memory_0_s1_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_cpu_0_data_master_qualified_request_onchip_memory_0_s1 OR internal_cpu_0_instruction_master_qualified_request_onchip_memory_0_s1));
  --assign onchip_memory_0_s1_readdata_from_sa = onchip_memory_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  onchip_memory_0_s1_readdata_from_sa <= onchip_memory_0_s1_readdata;
  internal_cpu_0_data_master_requests_onchip_memory_0_s1 <= to_std_logic(((Std_Logic_Vector'(cpu_0_data_master_address_to_slave(17 DOWNTO 15) & std_logic_vector'("000000000000000")) = std_logic_vector'("000000000000000000")))) AND ((cpu_0_data_master_read OR cpu_0_data_master_write));
  --registered rdv signal_name registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 assignment, which is an e_assign
  registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 <= cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register_in;
  --onchip_memory_0_s1_arb_share_counter set values, which is an e_mux
  onchip_memory_0_s1_arb_share_set_values <= std_logic'('1');
  --onchip_memory_0_s1_non_bursting_master_requests mux, which is an e_mux
  onchip_memory_0_s1_non_bursting_master_requests <= ((internal_cpu_0_data_master_requests_onchip_memory_0_s1 OR internal_cpu_0_instruction_master_requests_onchip_memory_0_s1) OR internal_cpu_0_data_master_requests_onchip_memory_0_s1) OR internal_cpu_0_instruction_master_requests_onchip_memory_0_s1;
  --onchip_memory_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  onchip_memory_0_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --onchip_memory_0_s1_arb_share_counter_next_value assignment, which is an e_assign
  onchip_memory_0_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(onchip_memory_0_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_memory_0_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(onchip_memory_0_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_memory_0_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --onchip_memory_0_s1_allgrants all slave grants, which is an e_mux
  onchip_memory_0_s1_allgrants <= ((or_reduce(onchip_memory_0_s1_grant_vector) OR or_reduce(onchip_memory_0_s1_grant_vector)) OR or_reduce(onchip_memory_0_s1_grant_vector)) OR or_reduce(onchip_memory_0_s1_grant_vector);
  --onchip_memory_0_s1_end_xfer assignment, which is an e_assign
  onchip_memory_0_s1_end_xfer <= NOT ((onchip_memory_0_s1_waits_for_read OR onchip_memory_0_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_onchip_memory_0_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_onchip_memory_0_s1 <= onchip_memory_0_s1_end_xfer AND (((NOT onchip_memory_0_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --onchip_memory_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  onchip_memory_0_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_onchip_memory_0_s1 AND onchip_memory_0_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_onchip_memory_0_s1 AND NOT onchip_memory_0_s1_non_bursting_master_requests));
  --onchip_memory_0_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_memory_0_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(onchip_memory_0_s1_arb_counter_enable) = '1' then 
        onchip_memory_0_s1_arb_share_counter <= onchip_memory_0_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --onchip_memory_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_memory_0_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((or_reduce(onchip_memory_0_s1_master_qreq_vector) AND end_xfer_arb_share_counter_term_onchip_memory_0_s1)) OR ((end_xfer_arb_share_counter_term_onchip_memory_0_s1 AND NOT onchip_memory_0_s1_non_bursting_master_requests)))) = '1' then 
        onchip_memory_0_s1_slavearbiterlockenable <= onchip_memory_0_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --cpu_0/data_master onchip_memory_0/s1 arbiterlock, which is an e_assign
  cpu_0_data_master_arbiterlock <= onchip_memory_0_s1_slavearbiterlockenable AND cpu_0_data_master_continuerequest;
  --onchip_memory_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  onchip_memory_0_s1_slavearbiterlockenable2 <= onchip_memory_0_s1_arb_share_counter_next_value;
  --cpu_0/data_master onchip_memory_0/s1 arbiterlock2, which is an e_assign
  cpu_0_data_master_arbiterlock2 <= onchip_memory_0_s1_slavearbiterlockenable2 AND cpu_0_data_master_continuerequest;
  --cpu_0/instruction_master onchip_memory_0/s1 arbiterlock, which is an e_assign
  cpu_0_instruction_master_arbiterlock <= onchip_memory_0_s1_slavearbiterlockenable AND cpu_0_instruction_master_continuerequest;
  --cpu_0/instruction_master onchip_memory_0/s1 arbiterlock2, which is an e_assign
  cpu_0_instruction_master_arbiterlock2 <= onchip_memory_0_s1_slavearbiterlockenable2 AND cpu_0_instruction_master_continuerequest;
  --cpu_0/instruction_master granted onchip_memory_0/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory_0_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory_0_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_0_instruction_master_saved_grant_onchip_memory_0_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((onchip_memory_0_s1_arbitration_holdoff_internal OR NOT internal_cpu_0_instruction_master_requests_onchip_memory_0_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory_0_s1))))));
      end if;
    end if;

  end process;

  --cpu_0_instruction_master_continuerequest continued request, which is an e_mux
  cpu_0_instruction_master_continuerequest <= last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory_0_s1 AND internal_cpu_0_instruction_master_requests_onchip_memory_0_s1;
  --onchip_memory_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
  onchip_memory_0_s1_any_continuerequest <= cpu_0_instruction_master_continuerequest OR cpu_0_data_master_continuerequest;
  internal_cpu_0_data_master_qualified_request_onchip_memory_0_s1 <= internal_cpu_0_data_master_requests_onchip_memory_0_s1 AND NOT (((((cpu_0_data_master_read AND (cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register))) OR (((NOT cpu_0_data_master_waitrequest) AND cpu_0_data_master_write))) OR cpu_0_instruction_master_arbiterlock));
  --cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register_in <= ((internal_cpu_0_data_master_granted_onchip_memory_0_s1 AND cpu_0_data_master_read) AND NOT onchip_memory_0_s1_waits_for_read) AND NOT (cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register);
  --shift register p1 cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register) & A_ToStdLogicVector(cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register_in)));
  --cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid cpu_0_data_master_read_data_valid_onchip_memory_0_s1, which is an e_mux
  cpu_0_data_master_read_data_valid_onchip_memory_0_s1 <= cpu_0_data_master_read_data_valid_onchip_memory_0_s1_shift_register;
  --onchip_memory_0_s1_writedata mux, which is an e_mux
  onchip_memory_0_s1_writedata <= cpu_0_data_master_writedata;
  --mux onchip_memory_0_s1_clken, which is an e_mux
  onchip_memory_0_s1_clken <= std_logic'('1');
  internal_cpu_0_instruction_master_requests_onchip_memory_0_s1 <= ((to_std_logic(((Std_Logic_Vector'(cpu_0_instruction_master_address_to_slave(17 DOWNTO 15) & std_logic_vector'("000000000000000")) = std_logic_vector'("000000000000000000")))) AND (cpu_0_instruction_master_read))) AND cpu_0_instruction_master_read;
  --cpu_0/data_master granted onchip_memory_0/s1 last time, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_cycle_cpu_0_data_master_granted_slave_onchip_memory_0_s1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        last_cycle_cpu_0_data_master_granted_slave_onchip_memory_0_s1 <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(cpu_0_data_master_saved_grant_onchip_memory_0_s1) = '1'), std_logic_vector'("00000000000000000000000000000001"), A_WE_StdLogicVector((std_logic'(((onchip_memory_0_s1_arbitration_holdoff_internal OR NOT internal_cpu_0_data_master_requests_onchip_memory_0_s1))) = '1'), std_logic_vector'("00000000000000000000000000000000"), (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(last_cycle_cpu_0_data_master_granted_slave_onchip_memory_0_s1))))));
      end if;
    end if;

  end process;

  --cpu_0_data_master_continuerequest continued request, which is an e_mux
  cpu_0_data_master_continuerequest <= last_cycle_cpu_0_data_master_granted_slave_onchip_memory_0_s1 AND internal_cpu_0_data_master_requests_onchip_memory_0_s1;
  internal_cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 <= internal_cpu_0_instruction_master_requests_onchip_memory_0_s1 AND NOT ((((cpu_0_instruction_master_read AND to_std_logic(((std_logic_vector'("00000000000000000000000000000001")<(std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_latency_counter)))))))) OR cpu_0_data_master_arbiterlock));
  --cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_in <= (internal_cpu_0_instruction_master_granted_onchip_memory_0_s1 AND cpu_0_instruction_master_read) AND NOT onchip_memory_0_s1_waits_for_read;
  --shift register p1 cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  p1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register <= Vector_To_Std_Logic(Std_Logic_Vector'(A_ToStdLogicVector(cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register) & A_ToStdLogicVector(cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register_in)));
  --cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register;
      end if;
    end if;

  end process;

  --local readdatavalid cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1, which is an e_mux
  cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 <= cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1_shift_register;
  --allow new arb cycle for onchip_memory_0/s1, which is an e_assign
  onchip_memory_0_s1_allow_new_arb_cycle <= NOT cpu_0_data_master_arbiterlock AND NOT cpu_0_instruction_master_arbiterlock;
  --cpu_0/instruction_master assignment into master qualified-requests vector for onchip_memory_0/s1, which is an e_assign
  onchip_memory_0_s1_master_qreq_vector(0) <= internal_cpu_0_instruction_master_qualified_request_onchip_memory_0_s1;
  --cpu_0/instruction_master grant onchip_memory_0/s1, which is an e_assign
  internal_cpu_0_instruction_master_granted_onchip_memory_0_s1 <= onchip_memory_0_s1_grant_vector(0);
  --cpu_0/instruction_master saved-grant onchip_memory_0/s1, which is an e_assign
  cpu_0_instruction_master_saved_grant_onchip_memory_0_s1 <= onchip_memory_0_s1_arb_winner(0) AND internal_cpu_0_instruction_master_requests_onchip_memory_0_s1;
  --cpu_0/data_master assignment into master qualified-requests vector for onchip_memory_0/s1, which is an e_assign
  onchip_memory_0_s1_master_qreq_vector(1) <= internal_cpu_0_data_master_qualified_request_onchip_memory_0_s1;
  --cpu_0/data_master grant onchip_memory_0/s1, which is an e_assign
  internal_cpu_0_data_master_granted_onchip_memory_0_s1 <= onchip_memory_0_s1_grant_vector(1);
  --cpu_0/data_master saved-grant onchip_memory_0/s1, which is an e_assign
  cpu_0_data_master_saved_grant_onchip_memory_0_s1 <= onchip_memory_0_s1_arb_winner(1) AND internal_cpu_0_data_master_requests_onchip_memory_0_s1;
  --onchip_memory_0/s1 chosen-master double-vector, which is an e_assign
  onchip_memory_0_s1_chosen_master_double_vector <= A_EXT (((std_logic_vector'("0") & ((onchip_memory_0_s1_master_qreq_vector & onchip_memory_0_s1_master_qreq_vector))) AND (((std_logic_vector'("0") & (Std_Logic_Vector'(NOT onchip_memory_0_s1_master_qreq_vector & NOT onchip_memory_0_s1_master_qreq_vector))) + (std_logic_vector'("000") & (onchip_memory_0_s1_arb_addend))))), 4);
  --stable onehot encoding of arb winner
  onchip_memory_0_s1_arb_winner <= A_WE_StdLogicVector((std_logic'(((onchip_memory_0_s1_allow_new_arb_cycle AND or_reduce(onchip_memory_0_s1_grant_vector)))) = '1'), onchip_memory_0_s1_grant_vector, onchip_memory_0_s1_saved_chosen_master_vector);
  --saved onchip_memory_0_s1_grant_vector, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_memory_0_s1_saved_chosen_master_vector <= std_logic_vector'("00");
    elsif clk'event and clk = '1' then
      if std_logic'(onchip_memory_0_s1_allow_new_arb_cycle) = '1' then 
        onchip_memory_0_s1_saved_chosen_master_vector <= A_WE_StdLogicVector((std_logic'(or_reduce(onchip_memory_0_s1_grant_vector)) = '1'), onchip_memory_0_s1_grant_vector, onchip_memory_0_s1_saved_chosen_master_vector);
      end if;
    end if;

  end process;

  --onehot encoding of chosen master
  onchip_memory_0_s1_grant_vector <= Std_Logic_Vector'(A_ToStdLogicVector(((onchip_memory_0_s1_chosen_master_double_vector(1) OR onchip_memory_0_s1_chosen_master_double_vector(3)))) & A_ToStdLogicVector(((onchip_memory_0_s1_chosen_master_double_vector(0) OR onchip_memory_0_s1_chosen_master_double_vector(2)))));
  --onchip_memory_0/s1 chosen master rotated left, which is an e_assign
  onchip_memory_0_s1_chosen_master_rot_left <= A_EXT (A_WE_StdLogicVector((((A_SLL(onchip_memory_0_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001")))) /= std_logic_vector'("00")), (std_logic_vector'("000000000000000000000000000000") & ((A_SLL(onchip_memory_0_s1_arb_winner,std_logic_vector'("00000000000000000000000000000001"))))), std_logic_vector'("00000000000000000000000000000001")), 2);
  --onchip_memory_0/s1's addend for next-master-grant
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      onchip_memory_0_s1_arb_addend <= std_logic_vector'("01");
    elsif clk'event and clk = '1' then
      if std_logic'(or_reduce(onchip_memory_0_s1_grant_vector)) = '1' then 
        onchip_memory_0_s1_arb_addend <= A_WE_StdLogicVector((std_logic'(onchip_memory_0_s1_end_xfer) = '1'), onchip_memory_0_s1_chosen_master_rot_left, onchip_memory_0_s1_grant_vector);
      end if;
    end if;

  end process;

  onchip_memory_0_s1_chipselect <= internal_cpu_0_data_master_granted_onchip_memory_0_s1 OR internal_cpu_0_instruction_master_granted_onchip_memory_0_s1;
  --onchip_memory_0_s1_firsttransfer first transaction, which is an e_assign
  onchip_memory_0_s1_firsttransfer <= NOT ((onchip_memory_0_s1_slavearbiterlockenable AND onchip_memory_0_s1_any_continuerequest));
  --onchip_memory_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  onchip_memory_0_s1_beginbursttransfer_internal <= onchip_memory_0_s1_begins_xfer;
  --onchip_memory_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  onchip_memory_0_s1_arbitration_holdoff_internal <= onchip_memory_0_s1_begins_xfer AND onchip_memory_0_s1_firsttransfer;
  --onchip_memory_0_s1_write assignment, which is an e_mux
  onchip_memory_0_s1_write <= internal_cpu_0_data_master_granted_onchip_memory_0_s1 AND cpu_0_data_master_write;
  shifted_address_to_onchip_memory_0_s1_from_cpu_0_data_master <= cpu_0_data_master_address_to_slave;
  --onchip_memory_0_s1_address mux, which is an e_mux
  onchip_memory_0_s1_address <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_onchip_memory_0_s1)) = '1'), (A_SRL(shifted_address_to_onchip_memory_0_s1_from_cpu_0_data_master,std_logic_vector'("00000000000000000000000000000010"))), (A_SRL(shifted_address_to_onchip_memory_0_s1_from_cpu_0_instruction_master,std_logic_vector'("00000000000000000000000000000010")))), 13);
  shifted_address_to_onchip_memory_0_s1_from_cpu_0_instruction_master <= cpu_0_instruction_master_address_to_slave;
  --d1_onchip_memory_0_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_onchip_memory_0_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_onchip_memory_0_s1_end_xfer <= onchip_memory_0_s1_end_xfer;
      end if;
    end if;

  end process;

  --onchip_memory_0_s1_waits_for_read in a cycle, which is an e_mux
  onchip_memory_0_s1_waits_for_read <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_memory_0_s1_in_a_read_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --onchip_memory_0_s1_in_a_read_cycle assignment, which is an e_assign
  onchip_memory_0_s1_in_a_read_cycle <= ((internal_cpu_0_data_master_granted_onchip_memory_0_s1 AND cpu_0_data_master_read)) OR ((internal_cpu_0_instruction_master_granted_onchip_memory_0_s1 AND cpu_0_instruction_master_read));
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= onchip_memory_0_s1_in_a_read_cycle;
  --onchip_memory_0_s1_waits_for_write in a cycle, which is an e_mux
  onchip_memory_0_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(onchip_memory_0_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --onchip_memory_0_s1_in_a_write_cycle assignment, which is an e_assign
  onchip_memory_0_s1_in_a_write_cycle <= internal_cpu_0_data_master_granted_onchip_memory_0_s1 AND cpu_0_data_master_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= onchip_memory_0_s1_in_a_write_cycle;
  wait_for_onchip_memory_0_s1_counter <= std_logic'('0');
  --onchip_memory_0_s1_byteenable byte enable port mux, which is an e_mux
  onchip_memory_0_s1_byteenable <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_cpu_0_data_master_granted_onchip_memory_0_s1)) = '1'), (std_logic_vector'("0000000000000000000000000000") & (cpu_0_data_master_byteenable)), -SIGNED(std_logic_vector'("00000000000000000000000000000001"))), 4);
  --vhdl renameroo for output signals
  cpu_0_data_master_granted_onchip_memory_0_s1 <= internal_cpu_0_data_master_granted_onchip_memory_0_s1;
  --vhdl renameroo for output signals
  cpu_0_data_master_qualified_request_onchip_memory_0_s1 <= internal_cpu_0_data_master_qualified_request_onchip_memory_0_s1;
  --vhdl renameroo for output signals
  cpu_0_data_master_requests_onchip_memory_0_s1 <= internal_cpu_0_data_master_requests_onchip_memory_0_s1;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_granted_onchip_memory_0_s1 <= internal_cpu_0_instruction_master_granted_onchip_memory_0_s1;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 <= internal_cpu_0_instruction_master_qualified_request_onchip_memory_0_s1;
  --vhdl renameroo for output signals
  cpu_0_instruction_master_requests_onchip_memory_0_s1 <= internal_cpu_0_instruction_master_requests_onchip_memory_0_s1;
--synthesis translate_off
    --grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line20 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_0_data_master_granted_onchip_memory_0_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(internal_cpu_0_instruction_master_granted_onchip_memory_0_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line20, now);
          write(write_line20, string'(": "));
          write(write_line20, string'("> 1 of grant signals are active simultaneously"));
          write(output, write_line20.all);
          deallocate (write_line20);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

    --saved_grant signals are active simultaneously, which is an e_process
    process (clk)
    VARIABLE write_line21 : line;
    begin
      if clk'event and clk = '1' then
        if (std_logic_vector'("000000000000000000000000000000") & (((std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_0_data_master_saved_grant_onchip_memory_0_s1))) + (std_logic_vector'("0") & (A_TOSTDLOGICVECTOR(cpu_0_instruction_master_saved_grant_onchip_memory_0_s1))))))>std_logic_vector'("00000000000000000000000000000001") then 
          write(write_line21, now);
          write(write_line21, string'(": "));
          write(write_line21, string'("> 1 of saved_grant signals are active simultaneously"));
          write(output, write_line21.all);
          deallocate (write_line21);
          assert false report "VHDL STOP" severity failure;
        end if;
      end if;

    end process;

--synthesis translate_on

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rcv_data_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_1_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_1_out_read : IN STD_LOGIC;
                 signal clock_1_out_write : IN STD_LOGIC;
                 signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rcv_data_s1_readdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_1_out_granted_rcv_data_s1 : OUT STD_LOGIC;
                 signal clock_1_out_qualified_request_rcv_data_s1 : OUT STD_LOGIC;
                 signal clock_1_out_read_data_valid_rcv_data_s1 : OUT STD_LOGIC;
                 signal clock_1_out_requests_rcv_data_s1 : OUT STD_LOGIC;
                 signal d1_rcv_data_s1_end_xfer : OUT STD_LOGIC;
                 signal rcv_data_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal rcv_data_s1_chipselect : OUT STD_LOGIC;
                 signal rcv_data_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal rcv_data_s1_reset_n : OUT STD_LOGIC;
                 signal rcv_data_s1_write_n : OUT STD_LOGIC;
                 signal rcv_data_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of rcv_data_s1_arbitrator : entity is FALSE;
end entity rcv_data_s1_arbitrator;


architecture europa of rcv_data_s1_arbitrator is
                signal clock_1_out_arbiterlock :  STD_LOGIC;
                signal clock_1_out_arbiterlock2 :  STD_LOGIC;
                signal clock_1_out_continuerequest :  STD_LOGIC;
                signal clock_1_out_saved_grant_rcv_data_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_rcv_data_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_1_out_granted_rcv_data_s1 :  STD_LOGIC;
                signal internal_clock_1_out_qualified_request_rcv_data_s1 :  STD_LOGIC;
                signal internal_clock_1_out_requests_rcv_data_s1 :  STD_LOGIC;
                signal rcv_data_s1_allgrants :  STD_LOGIC;
                signal rcv_data_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal rcv_data_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal rcv_data_s1_any_continuerequest :  STD_LOGIC;
                signal rcv_data_s1_arb_counter_enable :  STD_LOGIC;
                signal rcv_data_s1_arb_share_counter :  STD_LOGIC;
                signal rcv_data_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal rcv_data_s1_arb_share_set_values :  STD_LOGIC;
                signal rcv_data_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal rcv_data_s1_begins_xfer :  STD_LOGIC;
                signal rcv_data_s1_end_xfer :  STD_LOGIC;
                signal rcv_data_s1_firsttransfer :  STD_LOGIC;
                signal rcv_data_s1_grant_vector :  STD_LOGIC;
                signal rcv_data_s1_in_a_read_cycle :  STD_LOGIC;
                signal rcv_data_s1_in_a_write_cycle :  STD_LOGIC;
                signal rcv_data_s1_master_qreq_vector :  STD_LOGIC;
                signal rcv_data_s1_non_bursting_master_requests :  STD_LOGIC;
                signal rcv_data_s1_slavearbiterlockenable :  STD_LOGIC;
                signal rcv_data_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal rcv_data_s1_waits_for_read :  STD_LOGIC;
                signal rcv_data_s1_waits_for_write :  STD_LOGIC;
                signal wait_for_rcv_data_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT rcv_data_s1_end_xfer;
      end if;
    end if;

  end process;

  rcv_data_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_1_out_qualified_request_rcv_data_s1);
  --assign rcv_data_s1_readdata_from_sa = rcv_data_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  rcv_data_s1_readdata_from_sa <= rcv_data_s1_readdata;
  internal_clock_1_out_requests_rcv_data_s1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_1_out_read OR clock_1_out_write)))))));
  --rcv_data_s1_arb_share_counter set values, which is an e_mux
  rcv_data_s1_arb_share_set_values <= std_logic'('1');
  --rcv_data_s1_non_bursting_master_requests mux, which is an e_mux
  rcv_data_s1_non_bursting_master_requests <= internal_clock_1_out_requests_rcv_data_s1;
  --rcv_data_s1_any_bursting_master_saved_grant mux, which is an e_mux
  rcv_data_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --rcv_data_s1_arb_share_counter_next_value assignment, which is an e_assign
  rcv_data_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(rcv_data_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_data_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(rcv_data_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_data_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --rcv_data_s1_allgrants all slave grants, which is an e_mux
  rcv_data_s1_allgrants <= rcv_data_s1_grant_vector;
  --rcv_data_s1_end_xfer assignment, which is an e_assign
  rcv_data_s1_end_xfer <= NOT ((rcv_data_s1_waits_for_read OR rcv_data_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_rcv_data_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_rcv_data_s1 <= rcv_data_s1_end_xfer AND (((NOT rcv_data_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --rcv_data_s1_arb_share_counter arbitration counter enable, which is an e_assign
  rcv_data_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_rcv_data_s1 AND rcv_data_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_rcv_data_s1 AND NOT rcv_data_s1_non_bursting_master_requests));
  --rcv_data_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      rcv_data_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(rcv_data_s1_arb_counter_enable) = '1' then 
        rcv_data_s1_arb_share_counter <= rcv_data_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --rcv_data_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      rcv_data_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((rcv_data_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_rcv_data_s1)) OR ((end_xfer_arb_share_counter_term_rcv_data_s1 AND NOT rcv_data_s1_non_bursting_master_requests)))) = '1' then 
        rcv_data_s1_slavearbiterlockenable <= rcv_data_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_1/out rcv_data/s1 arbiterlock, which is an e_assign
  clock_1_out_arbiterlock <= rcv_data_s1_slavearbiterlockenable AND clock_1_out_continuerequest;
  --rcv_data_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  rcv_data_s1_slavearbiterlockenable2 <= rcv_data_s1_arb_share_counter_next_value;
  --clock_1/out rcv_data/s1 arbiterlock2, which is an e_assign
  clock_1_out_arbiterlock2 <= rcv_data_s1_slavearbiterlockenable2 AND clock_1_out_continuerequest;
  --rcv_data_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  rcv_data_s1_any_continuerequest <= std_logic'('1');
  --clock_1_out_continuerequest continued request, which is an e_assign
  clock_1_out_continuerequest <= std_logic'('1');
  internal_clock_1_out_qualified_request_rcv_data_s1 <= internal_clock_1_out_requests_rcv_data_s1;
  --rcv_data_s1_writedata mux, which is an e_mux
  rcv_data_s1_writedata <= clock_1_out_writedata (3 DOWNTO 0);
  --master is always granted when requested
  internal_clock_1_out_granted_rcv_data_s1 <= internal_clock_1_out_qualified_request_rcv_data_s1;
  --clock_1/out saved-grant rcv_data/s1, which is an e_assign
  clock_1_out_saved_grant_rcv_data_s1 <= internal_clock_1_out_requests_rcv_data_s1;
  --allow new arb cycle for rcv_data/s1, which is an e_assign
  rcv_data_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  rcv_data_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  rcv_data_s1_master_qreq_vector <= std_logic'('1');
  --rcv_data_s1_reset_n assignment, which is an e_assign
  rcv_data_s1_reset_n <= reset_n;
  rcv_data_s1_chipselect <= internal_clock_1_out_granted_rcv_data_s1;
  --rcv_data_s1_firsttransfer first transaction, which is an e_assign
  rcv_data_s1_firsttransfer <= NOT ((rcv_data_s1_slavearbiterlockenable AND rcv_data_s1_any_continuerequest));
  --rcv_data_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  rcv_data_s1_beginbursttransfer_internal <= rcv_data_s1_begins_xfer;
  --~rcv_data_s1_write_n assignment, which is an e_mux
  rcv_data_s1_write_n <= NOT ((internal_clock_1_out_granted_rcv_data_s1 AND clock_1_out_write));
  --rcv_data_s1_address mux, which is an e_mux
  rcv_data_s1_address <= clock_1_out_nativeaddress;
  --d1_rcv_data_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_rcv_data_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_rcv_data_s1_end_xfer <= rcv_data_s1_end_xfer;
      end if;
    end if;

  end process;

  --rcv_data_s1_waits_for_read in a cycle, which is an e_mux
  rcv_data_s1_waits_for_read <= rcv_data_s1_in_a_read_cycle AND rcv_data_s1_begins_xfer;
  --rcv_data_s1_in_a_read_cycle assignment, which is an e_assign
  rcv_data_s1_in_a_read_cycle <= internal_clock_1_out_granted_rcv_data_s1 AND clock_1_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= rcv_data_s1_in_a_read_cycle;
  --rcv_data_s1_waits_for_write in a cycle, which is an e_mux
  rcv_data_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_data_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --rcv_data_s1_in_a_write_cycle assignment, which is an e_assign
  rcv_data_s1_in_a_write_cycle <= internal_clock_1_out_granted_rcv_data_s1 AND clock_1_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= rcv_data_s1_in_a_write_cycle;
  wait_for_rcv_data_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_1_out_granted_rcv_data_s1 <= internal_clock_1_out_granted_rcv_data_s1;
  --vhdl renameroo for output signals
  clock_1_out_qualified_request_rcv_data_s1 <= internal_clock_1_out_qualified_request_rcv_data_s1;
  --vhdl renameroo for output signals
  clock_1_out_requests_rcv_data_s1 <= internal_clock_1_out_requests_rcv_data_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rcv_dv_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_0_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_0_out_read : IN STD_LOGIC;
                 signal clock_0_out_write : IN STD_LOGIC;
                 signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rcv_dv_s1_readdata : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_0_out_granted_rcv_dv_s1 : OUT STD_LOGIC;
                 signal clock_0_out_qualified_request_rcv_dv_s1 : OUT STD_LOGIC;
                 signal clock_0_out_read_data_valid_rcv_dv_s1 : OUT STD_LOGIC;
                 signal clock_0_out_requests_rcv_dv_s1 : OUT STD_LOGIC;
                 signal d1_rcv_dv_s1_end_xfer : OUT STD_LOGIC;
                 signal rcv_dv_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal rcv_dv_s1_chipselect : OUT STD_LOGIC;
                 signal rcv_dv_s1_readdata_from_sa : OUT STD_LOGIC;
                 signal rcv_dv_s1_reset_n : OUT STD_LOGIC;
                 signal rcv_dv_s1_write_n : OUT STD_LOGIC;
                 signal rcv_dv_s1_writedata : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of rcv_dv_s1_arbitrator : entity is FALSE;
end entity rcv_dv_s1_arbitrator;


architecture europa of rcv_dv_s1_arbitrator is
                signal clock_0_out_arbiterlock :  STD_LOGIC;
                signal clock_0_out_arbiterlock2 :  STD_LOGIC;
                signal clock_0_out_continuerequest :  STD_LOGIC;
                signal clock_0_out_saved_grant_rcv_dv_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_rcv_dv_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_0_out_granted_rcv_dv_s1 :  STD_LOGIC;
                signal internal_clock_0_out_qualified_request_rcv_dv_s1 :  STD_LOGIC;
                signal internal_clock_0_out_requests_rcv_dv_s1 :  STD_LOGIC;
                signal rcv_dv_s1_allgrants :  STD_LOGIC;
                signal rcv_dv_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal rcv_dv_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal rcv_dv_s1_any_continuerequest :  STD_LOGIC;
                signal rcv_dv_s1_arb_counter_enable :  STD_LOGIC;
                signal rcv_dv_s1_arb_share_counter :  STD_LOGIC;
                signal rcv_dv_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal rcv_dv_s1_arb_share_set_values :  STD_LOGIC;
                signal rcv_dv_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal rcv_dv_s1_begins_xfer :  STD_LOGIC;
                signal rcv_dv_s1_end_xfer :  STD_LOGIC;
                signal rcv_dv_s1_firsttransfer :  STD_LOGIC;
                signal rcv_dv_s1_grant_vector :  STD_LOGIC;
                signal rcv_dv_s1_in_a_read_cycle :  STD_LOGIC;
                signal rcv_dv_s1_in_a_write_cycle :  STD_LOGIC;
                signal rcv_dv_s1_master_qreq_vector :  STD_LOGIC;
                signal rcv_dv_s1_non_bursting_master_requests :  STD_LOGIC;
                signal rcv_dv_s1_slavearbiterlockenable :  STD_LOGIC;
                signal rcv_dv_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal rcv_dv_s1_waits_for_read :  STD_LOGIC;
                signal rcv_dv_s1_waits_for_write :  STD_LOGIC;
                signal wait_for_rcv_dv_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT rcv_dv_s1_end_xfer;
      end if;
    end if;

  end process;

  rcv_dv_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_0_out_qualified_request_rcv_dv_s1);
  --assign rcv_dv_s1_readdata_from_sa = rcv_dv_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  rcv_dv_s1_readdata_from_sa <= rcv_dv_s1_readdata;
  internal_clock_0_out_requests_rcv_dv_s1 <= Vector_To_Std_Logic(((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_0_out_read OR clock_0_out_write)))))));
  --rcv_dv_s1_arb_share_counter set values, which is an e_mux
  rcv_dv_s1_arb_share_set_values <= std_logic'('1');
  --rcv_dv_s1_non_bursting_master_requests mux, which is an e_mux
  rcv_dv_s1_non_bursting_master_requests <= internal_clock_0_out_requests_rcv_dv_s1;
  --rcv_dv_s1_any_bursting_master_saved_grant mux, which is an e_mux
  rcv_dv_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --rcv_dv_s1_arb_share_counter_next_value assignment, which is an e_assign
  rcv_dv_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(rcv_dv_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_dv_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(rcv_dv_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_dv_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --rcv_dv_s1_allgrants all slave grants, which is an e_mux
  rcv_dv_s1_allgrants <= rcv_dv_s1_grant_vector;
  --rcv_dv_s1_end_xfer assignment, which is an e_assign
  rcv_dv_s1_end_xfer <= NOT ((rcv_dv_s1_waits_for_read OR rcv_dv_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_rcv_dv_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_rcv_dv_s1 <= rcv_dv_s1_end_xfer AND (((NOT rcv_dv_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --rcv_dv_s1_arb_share_counter arbitration counter enable, which is an e_assign
  rcv_dv_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_rcv_dv_s1 AND rcv_dv_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_rcv_dv_s1 AND NOT rcv_dv_s1_non_bursting_master_requests));
  --rcv_dv_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      rcv_dv_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(rcv_dv_s1_arb_counter_enable) = '1' then 
        rcv_dv_s1_arb_share_counter <= rcv_dv_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --rcv_dv_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      rcv_dv_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((rcv_dv_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_rcv_dv_s1)) OR ((end_xfer_arb_share_counter_term_rcv_dv_s1 AND NOT rcv_dv_s1_non_bursting_master_requests)))) = '1' then 
        rcv_dv_s1_slavearbiterlockenable <= rcv_dv_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_0/out rcv_dv/s1 arbiterlock, which is an e_assign
  clock_0_out_arbiterlock <= rcv_dv_s1_slavearbiterlockenable AND clock_0_out_continuerequest;
  --rcv_dv_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  rcv_dv_s1_slavearbiterlockenable2 <= rcv_dv_s1_arb_share_counter_next_value;
  --clock_0/out rcv_dv/s1 arbiterlock2, which is an e_assign
  clock_0_out_arbiterlock2 <= rcv_dv_s1_slavearbiterlockenable2 AND clock_0_out_continuerequest;
  --rcv_dv_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  rcv_dv_s1_any_continuerequest <= std_logic'('1');
  --clock_0_out_continuerequest continued request, which is an e_assign
  clock_0_out_continuerequest <= std_logic'('1');
  internal_clock_0_out_qualified_request_rcv_dv_s1 <= internal_clock_0_out_requests_rcv_dv_s1;
  --rcv_dv_s1_writedata mux, which is an e_mux
  rcv_dv_s1_writedata <= clock_0_out_writedata(0);
  --master is always granted when requested
  internal_clock_0_out_granted_rcv_dv_s1 <= internal_clock_0_out_qualified_request_rcv_dv_s1;
  --clock_0/out saved-grant rcv_dv/s1, which is an e_assign
  clock_0_out_saved_grant_rcv_dv_s1 <= internal_clock_0_out_requests_rcv_dv_s1;
  --allow new arb cycle for rcv_dv/s1, which is an e_assign
  rcv_dv_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  rcv_dv_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  rcv_dv_s1_master_qreq_vector <= std_logic'('1');
  --rcv_dv_s1_reset_n assignment, which is an e_assign
  rcv_dv_s1_reset_n <= reset_n;
  rcv_dv_s1_chipselect <= internal_clock_0_out_granted_rcv_dv_s1;
  --rcv_dv_s1_firsttransfer first transaction, which is an e_assign
  rcv_dv_s1_firsttransfer <= NOT ((rcv_dv_s1_slavearbiterlockenable AND rcv_dv_s1_any_continuerequest));
  --rcv_dv_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  rcv_dv_s1_beginbursttransfer_internal <= rcv_dv_s1_begins_xfer;
  --~rcv_dv_s1_write_n assignment, which is an e_mux
  rcv_dv_s1_write_n <= NOT ((internal_clock_0_out_granted_rcv_dv_s1 AND clock_0_out_write));
  --rcv_dv_s1_address mux, which is an e_mux
  rcv_dv_s1_address <= clock_0_out_nativeaddress;
  --d1_rcv_dv_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_rcv_dv_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_rcv_dv_s1_end_xfer <= rcv_dv_s1_end_xfer;
      end if;
    end if;

  end process;

  --rcv_dv_s1_waits_for_read in a cycle, which is an e_mux
  rcv_dv_s1_waits_for_read <= rcv_dv_s1_in_a_read_cycle AND rcv_dv_s1_begins_xfer;
  --rcv_dv_s1_in_a_read_cycle assignment, which is an e_assign
  rcv_dv_s1_in_a_read_cycle <= internal_clock_0_out_granted_rcv_dv_s1 AND clock_0_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= rcv_dv_s1_in_a_read_cycle;
  --rcv_dv_s1_waits_for_write in a cycle, which is an e_mux
  rcv_dv_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(rcv_dv_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --rcv_dv_s1_in_a_write_cycle assignment, which is an e_assign
  rcv_dv_s1_in_a_write_cycle <= internal_clock_0_out_granted_rcv_dv_s1 AND clock_0_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= rcv_dv_s1_in_a_write_cycle;
  wait_for_rcv_dv_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_0_out_granted_rcv_dv_s1 <= internal_clock_0_out_granted_rcv_dv_s1;
  --vhdl renameroo for output signals
  clock_0_out_qualified_request_rcv_dv_s1 <= internal_clock_0_out_qualified_request_rcv_dv_s1;
  --vhdl renameroo for output signals
  clock_0_out_requests_rcv_dv_s1 <= internal_clock_0_out_requests_rcv_dv_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xmt_data_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_3_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_3_out_read : IN STD_LOGIC;
                 signal clock_3_out_write : IN STD_LOGIC;
                 signal clock_3_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_3_out_granted_xmt_data_s1 : OUT STD_LOGIC;
                 signal clock_3_out_qualified_request_xmt_data_s1 : OUT STD_LOGIC;
                 signal clock_3_out_read_data_valid_xmt_data_s1 : OUT STD_LOGIC;
                 signal clock_3_out_requests_xmt_data_s1 : OUT STD_LOGIC;
                 signal d1_xmt_data_s1_end_xfer : OUT STD_LOGIC;
                 signal xmt_data_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal xmt_data_s1_chipselect : OUT STD_LOGIC;
                 signal xmt_data_s1_reset_n : OUT STD_LOGIC;
                 signal xmt_data_s1_write_n : OUT STD_LOGIC;
                 signal xmt_data_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of xmt_data_s1_arbitrator : entity is FALSE;
end entity xmt_data_s1_arbitrator;


architecture europa of xmt_data_s1_arbitrator is
                signal clock_3_out_arbiterlock :  STD_LOGIC;
                signal clock_3_out_arbiterlock2 :  STD_LOGIC;
                signal clock_3_out_continuerequest :  STD_LOGIC;
                signal clock_3_out_saved_grant_xmt_data_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_xmt_data_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_3_out_granted_xmt_data_s1 :  STD_LOGIC;
                signal internal_clock_3_out_qualified_request_xmt_data_s1 :  STD_LOGIC;
                signal internal_clock_3_out_requests_xmt_data_s1 :  STD_LOGIC;
                signal wait_for_xmt_data_s1_counter :  STD_LOGIC;
                signal xmt_data_s1_allgrants :  STD_LOGIC;
                signal xmt_data_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal xmt_data_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal xmt_data_s1_any_continuerequest :  STD_LOGIC;
                signal xmt_data_s1_arb_counter_enable :  STD_LOGIC;
                signal xmt_data_s1_arb_share_counter :  STD_LOGIC;
                signal xmt_data_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal xmt_data_s1_arb_share_set_values :  STD_LOGIC;
                signal xmt_data_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal xmt_data_s1_begins_xfer :  STD_LOGIC;
                signal xmt_data_s1_end_xfer :  STD_LOGIC;
                signal xmt_data_s1_firsttransfer :  STD_LOGIC;
                signal xmt_data_s1_grant_vector :  STD_LOGIC;
                signal xmt_data_s1_in_a_read_cycle :  STD_LOGIC;
                signal xmt_data_s1_in_a_write_cycle :  STD_LOGIC;
                signal xmt_data_s1_master_qreq_vector :  STD_LOGIC;
                signal xmt_data_s1_non_bursting_master_requests :  STD_LOGIC;
                signal xmt_data_s1_slavearbiterlockenable :  STD_LOGIC;
                signal xmt_data_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal xmt_data_s1_waits_for_read :  STD_LOGIC;
                signal xmt_data_s1_waits_for_write :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT xmt_data_s1_end_xfer;
      end if;
    end if;

  end process;

  xmt_data_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_3_out_qualified_request_xmt_data_s1);
  internal_clock_3_out_requests_xmt_data_s1 <= Vector_To_Std_Logic(((((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_3_out_read OR clock_3_out_write))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_3_out_write)))));
  --xmt_data_s1_arb_share_counter set values, which is an e_mux
  xmt_data_s1_arb_share_set_values <= std_logic'('1');
  --xmt_data_s1_non_bursting_master_requests mux, which is an e_mux
  xmt_data_s1_non_bursting_master_requests <= internal_clock_3_out_requests_xmt_data_s1;
  --xmt_data_s1_any_bursting_master_saved_grant mux, which is an e_mux
  xmt_data_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --xmt_data_s1_arb_share_counter_next_value assignment, which is an e_assign
  xmt_data_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(xmt_data_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_data_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(xmt_data_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_data_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --xmt_data_s1_allgrants all slave grants, which is an e_mux
  xmt_data_s1_allgrants <= xmt_data_s1_grant_vector;
  --xmt_data_s1_end_xfer assignment, which is an e_assign
  xmt_data_s1_end_xfer <= NOT ((xmt_data_s1_waits_for_read OR xmt_data_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_xmt_data_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_xmt_data_s1 <= xmt_data_s1_end_xfer AND (((NOT xmt_data_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --xmt_data_s1_arb_share_counter arbitration counter enable, which is an e_assign
  xmt_data_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_xmt_data_s1 AND xmt_data_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_xmt_data_s1 AND NOT xmt_data_s1_non_bursting_master_requests));
  --xmt_data_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      xmt_data_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(xmt_data_s1_arb_counter_enable) = '1' then 
        xmt_data_s1_arb_share_counter <= xmt_data_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --xmt_data_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      xmt_data_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((xmt_data_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_xmt_data_s1)) OR ((end_xfer_arb_share_counter_term_xmt_data_s1 AND NOT xmt_data_s1_non_bursting_master_requests)))) = '1' then 
        xmt_data_s1_slavearbiterlockenable <= xmt_data_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_3/out xmt_data/s1 arbiterlock, which is an e_assign
  clock_3_out_arbiterlock <= xmt_data_s1_slavearbiterlockenable AND clock_3_out_continuerequest;
  --xmt_data_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  xmt_data_s1_slavearbiterlockenable2 <= xmt_data_s1_arb_share_counter_next_value;
  --clock_3/out xmt_data/s1 arbiterlock2, which is an e_assign
  clock_3_out_arbiterlock2 <= xmt_data_s1_slavearbiterlockenable2 AND clock_3_out_continuerequest;
  --xmt_data_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  xmt_data_s1_any_continuerequest <= std_logic'('1');
  --clock_3_out_continuerequest continued request, which is an e_assign
  clock_3_out_continuerequest <= std_logic'('1');
  internal_clock_3_out_qualified_request_xmt_data_s1 <= internal_clock_3_out_requests_xmt_data_s1;
  --xmt_data_s1_writedata mux, which is an e_mux
  xmt_data_s1_writedata <= clock_3_out_writedata (3 DOWNTO 0);
  --master is always granted when requested
  internal_clock_3_out_granted_xmt_data_s1 <= internal_clock_3_out_qualified_request_xmt_data_s1;
  --clock_3/out saved-grant xmt_data/s1, which is an e_assign
  clock_3_out_saved_grant_xmt_data_s1 <= internal_clock_3_out_requests_xmt_data_s1;
  --allow new arb cycle for xmt_data/s1, which is an e_assign
  xmt_data_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  xmt_data_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  xmt_data_s1_master_qreq_vector <= std_logic'('1');
  --xmt_data_s1_reset_n assignment, which is an e_assign
  xmt_data_s1_reset_n <= reset_n;
  xmt_data_s1_chipselect <= internal_clock_3_out_granted_xmt_data_s1;
  --xmt_data_s1_firsttransfer first transaction, which is an e_assign
  xmt_data_s1_firsttransfer <= NOT ((xmt_data_s1_slavearbiterlockenable AND xmt_data_s1_any_continuerequest));
  --xmt_data_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  xmt_data_s1_beginbursttransfer_internal <= xmt_data_s1_begins_xfer;
  --~xmt_data_s1_write_n assignment, which is an e_mux
  xmt_data_s1_write_n <= NOT ((internal_clock_3_out_granted_xmt_data_s1 AND clock_3_out_write));
  --xmt_data_s1_address mux, which is an e_mux
  xmt_data_s1_address <= clock_3_out_nativeaddress;
  --d1_xmt_data_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_xmt_data_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_xmt_data_s1_end_xfer <= xmt_data_s1_end_xfer;
      end if;
    end if;

  end process;

  --xmt_data_s1_waits_for_read in a cycle, which is an e_mux
  xmt_data_s1_waits_for_read <= xmt_data_s1_in_a_read_cycle AND xmt_data_s1_begins_xfer;
  --xmt_data_s1_in_a_read_cycle assignment, which is an e_assign
  xmt_data_s1_in_a_read_cycle <= internal_clock_3_out_granted_xmt_data_s1 AND clock_3_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= xmt_data_s1_in_a_read_cycle;
  --xmt_data_s1_waits_for_write in a cycle, which is an e_mux
  xmt_data_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_data_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --xmt_data_s1_in_a_write_cycle assignment, which is an e_assign
  xmt_data_s1_in_a_write_cycle <= internal_clock_3_out_granted_xmt_data_s1 AND clock_3_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= xmt_data_s1_in_a_write_cycle;
  wait_for_xmt_data_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_3_out_granted_xmt_data_s1 <= internal_clock_3_out_granted_xmt_data_s1;
  --vhdl renameroo for output signals
  clock_3_out_qualified_request_xmt_data_s1 <= internal_clock_3_out_qualified_request_xmt_data_s1;
  --vhdl renameroo for output signals
  clock_3_out_requests_xmt_data_s1 <= internal_clock_3_out_requests_xmt_data_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xmt_dv_s1_arbitrator is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clock_2_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clock_2_out_read : IN STD_LOGIC;
                 signal clock_2_out_write : IN STD_LOGIC;
                 signal clock_2_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal clock_2_out_granted_xmt_dv_s1 : OUT STD_LOGIC;
                 signal clock_2_out_qualified_request_xmt_dv_s1 : OUT STD_LOGIC;
                 signal clock_2_out_read_data_valid_xmt_dv_s1 : OUT STD_LOGIC;
                 signal clock_2_out_requests_xmt_dv_s1 : OUT STD_LOGIC;
                 signal d1_xmt_dv_s1_end_xfer : OUT STD_LOGIC;
                 signal xmt_dv_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal xmt_dv_s1_chipselect : OUT STD_LOGIC;
                 signal xmt_dv_s1_reset_n : OUT STD_LOGIC;
                 signal xmt_dv_s1_write_n : OUT STD_LOGIC;
                 signal xmt_dv_s1_writedata : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of xmt_dv_s1_arbitrator : entity is FALSE;
end entity xmt_dv_s1_arbitrator;


architecture europa of xmt_dv_s1_arbitrator is
                signal clock_2_out_arbiterlock :  STD_LOGIC;
                signal clock_2_out_arbiterlock2 :  STD_LOGIC;
                signal clock_2_out_continuerequest :  STD_LOGIC;
                signal clock_2_out_saved_grant_xmt_dv_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal end_xfer_arb_share_counter_term_xmt_dv_s1 :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_clock_2_out_granted_xmt_dv_s1 :  STD_LOGIC;
                signal internal_clock_2_out_qualified_request_xmt_dv_s1 :  STD_LOGIC;
                signal internal_clock_2_out_requests_xmt_dv_s1 :  STD_LOGIC;
                signal wait_for_xmt_dv_s1_counter :  STD_LOGIC;
                signal xmt_dv_s1_allgrants :  STD_LOGIC;
                signal xmt_dv_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal xmt_dv_s1_any_bursting_master_saved_grant :  STD_LOGIC;
                signal xmt_dv_s1_any_continuerequest :  STD_LOGIC;
                signal xmt_dv_s1_arb_counter_enable :  STD_LOGIC;
                signal xmt_dv_s1_arb_share_counter :  STD_LOGIC;
                signal xmt_dv_s1_arb_share_counter_next_value :  STD_LOGIC;
                signal xmt_dv_s1_arb_share_set_values :  STD_LOGIC;
                signal xmt_dv_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal xmt_dv_s1_begins_xfer :  STD_LOGIC;
                signal xmt_dv_s1_end_xfer :  STD_LOGIC;
                signal xmt_dv_s1_firsttransfer :  STD_LOGIC;
                signal xmt_dv_s1_grant_vector :  STD_LOGIC;
                signal xmt_dv_s1_in_a_read_cycle :  STD_LOGIC;
                signal xmt_dv_s1_in_a_write_cycle :  STD_LOGIC;
                signal xmt_dv_s1_master_qreq_vector :  STD_LOGIC;
                signal xmt_dv_s1_non_bursting_master_requests :  STD_LOGIC;
                signal xmt_dv_s1_slavearbiterlockenable :  STD_LOGIC;
                signal xmt_dv_s1_slavearbiterlockenable2 :  STD_LOGIC;
                signal xmt_dv_s1_waits_for_read :  STD_LOGIC;
                signal xmt_dv_s1_waits_for_write :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT xmt_dv_s1_end_xfer;
      end if;
    end if;

  end process;

  xmt_dv_s1_begins_xfer <= NOT d1_reasons_to_wait AND (internal_clock_2_out_qualified_request_xmt_dv_s1);
  internal_clock_2_out_requests_xmt_dv_s1 <= Vector_To_Std_Logic(((((std_logic_vector'("00000000000000000000000000000001")) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(((clock_2_out_read OR clock_2_out_write))))))) AND (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(clock_2_out_write)))));
  --xmt_dv_s1_arb_share_counter set values, which is an e_mux
  xmt_dv_s1_arb_share_set_values <= std_logic'('1');
  --xmt_dv_s1_non_bursting_master_requests mux, which is an e_mux
  xmt_dv_s1_non_bursting_master_requests <= internal_clock_2_out_requests_xmt_dv_s1;
  --xmt_dv_s1_any_bursting_master_saved_grant mux, which is an e_mux
  xmt_dv_s1_any_bursting_master_saved_grant <= std_logic'('0');
  --xmt_dv_s1_arb_share_counter_next_value assignment, which is an e_assign
  xmt_dv_s1_arb_share_counter_next_value <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(xmt_dv_s1_firsttransfer) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_dv_s1_arb_share_set_values))) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(xmt_dv_s1_arb_share_counter) = '1'), (((std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_dv_s1_arb_share_counter))) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))));
  --xmt_dv_s1_allgrants all slave grants, which is an e_mux
  xmt_dv_s1_allgrants <= xmt_dv_s1_grant_vector;
  --xmt_dv_s1_end_xfer assignment, which is an e_assign
  xmt_dv_s1_end_xfer <= NOT ((xmt_dv_s1_waits_for_read OR xmt_dv_s1_waits_for_write));
  --end_xfer_arb_share_counter_term_xmt_dv_s1 arb share counter enable term, which is an e_assign
  end_xfer_arb_share_counter_term_xmt_dv_s1 <= xmt_dv_s1_end_xfer AND (((NOT xmt_dv_s1_any_bursting_master_saved_grant OR in_a_read_cycle) OR in_a_write_cycle));
  --xmt_dv_s1_arb_share_counter arbitration counter enable, which is an e_assign
  xmt_dv_s1_arb_counter_enable <= ((end_xfer_arb_share_counter_term_xmt_dv_s1 AND xmt_dv_s1_allgrants)) OR ((end_xfer_arb_share_counter_term_xmt_dv_s1 AND NOT xmt_dv_s1_non_bursting_master_requests));
  --xmt_dv_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      xmt_dv_s1_arb_share_counter <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'(xmt_dv_s1_arb_counter_enable) = '1' then 
        xmt_dv_s1_arb_share_counter <= xmt_dv_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --xmt_dv_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      xmt_dv_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((((xmt_dv_s1_master_qreq_vector AND end_xfer_arb_share_counter_term_xmt_dv_s1)) OR ((end_xfer_arb_share_counter_term_xmt_dv_s1 AND NOT xmt_dv_s1_non_bursting_master_requests)))) = '1' then 
        xmt_dv_s1_slavearbiterlockenable <= xmt_dv_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --clock_2/out xmt_dv/s1 arbiterlock, which is an e_assign
  clock_2_out_arbiterlock <= xmt_dv_s1_slavearbiterlockenable AND clock_2_out_continuerequest;
  --xmt_dv_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  xmt_dv_s1_slavearbiterlockenable2 <= xmt_dv_s1_arb_share_counter_next_value;
  --clock_2/out xmt_dv/s1 arbiterlock2, which is an e_assign
  clock_2_out_arbiterlock2 <= xmt_dv_s1_slavearbiterlockenable2 AND clock_2_out_continuerequest;
  --xmt_dv_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  xmt_dv_s1_any_continuerequest <= std_logic'('1');
  --clock_2_out_continuerequest continued request, which is an e_assign
  clock_2_out_continuerequest <= std_logic'('1');
  internal_clock_2_out_qualified_request_xmt_dv_s1 <= internal_clock_2_out_requests_xmt_dv_s1;
  --xmt_dv_s1_writedata mux, which is an e_mux
  xmt_dv_s1_writedata <= clock_2_out_writedata(0);
  --master is always granted when requested
  internal_clock_2_out_granted_xmt_dv_s1 <= internal_clock_2_out_qualified_request_xmt_dv_s1;
  --clock_2/out saved-grant xmt_dv/s1, which is an e_assign
  clock_2_out_saved_grant_xmt_dv_s1 <= internal_clock_2_out_requests_xmt_dv_s1;
  --allow new arb cycle for xmt_dv/s1, which is an e_assign
  xmt_dv_s1_allow_new_arb_cycle <= std_logic'('1');
  --placeholder chosen master
  xmt_dv_s1_grant_vector <= std_logic'('1');
  --placeholder vector of master qualified-requests
  xmt_dv_s1_master_qreq_vector <= std_logic'('1');
  --xmt_dv_s1_reset_n assignment, which is an e_assign
  xmt_dv_s1_reset_n <= reset_n;
  xmt_dv_s1_chipselect <= internal_clock_2_out_granted_xmt_dv_s1;
  --xmt_dv_s1_firsttransfer first transaction, which is an e_assign
  xmt_dv_s1_firsttransfer <= NOT ((xmt_dv_s1_slavearbiterlockenable AND xmt_dv_s1_any_continuerequest));
  --xmt_dv_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  xmt_dv_s1_beginbursttransfer_internal <= xmt_dv_s1_begins_xfer;
  --~xmt_dv_s1_write_n assignment, which is an e_mux
  xmt_dv_s1_write_n <= NOT ((internal_clock_2_out_granted_xmt_dv_s1 AND clock_2_out_write));
  --xmt_dv_s1_address mux, which is an e_mux
  xmt_dv_s1_address <= clock_2_out_nativeaddress;
  --d1_xmt_dv_s1_end_xfer register, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_xmt_dv_s1_end_xfer <= std_logic'('1');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_xmt_dv_s1_end_xfer <= xmt_dv_s1_end_xfer;
      end if;
    end if;

  end process;

  --xmt_dv_s1_waits_for_read in a cycle, which is an e_mux
  xmt_dv_s1_waits_for_read <= xmt_dv_s1_in_a_read_cycle AND xmt_dv_s1_begins_xfer;
  --xmt_dv_s1_in_a_read_cycle assignment, which is an e_assign
  xmt_dv_s1_in_a_read_cycle <= internal_clock_2_out_granted_xmt_dv_s1 AND clock_2_out_read;
  --in_a_read_cycle assignment, which is an e_mux
  in_a_read_cycle <= xmt_dv_s1_in_a_read_cycle;
  --xmt_dv_s1_waits_for_write in a cycle, which is an e_mux
  xmt_dv_s1_waits_for_write <= Vector_To_Std_Logic(((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(xmt_dv_s1_in_a_write_cycle))) AND std_logic_vector'("00000000000000000000000000000000")));
  --xmt_dv_s1_in_a_write_cycle assignment, which is an e_assign
  xmt_dv_s1_in_a_write_cycle <= internal_clock_2_out_granted_xmt_dv_s1 AND clock_2_out_write;
  --in_a_write_cycle assignment, which is an e_mux
  in_a_write_cycle <= xmt_dv_s1_in_a_write_cycle;
  wait_for_xmt_dv_s1_counter <= std_logic'('0');
  --vhdl renameroo for output signals
  clock_2_out_granted_xmt_dv_s1 <= internal_clock_2_out_granted_xmt_dv_s1;
  --vhdl renameroo for output signals
  clock_2_out_qualified_request_xmt_dv_s1 <= internal_clock_2_out_qualified_request_xmt_dv_s1;
  --vhdl renameroo for output signals
  clock_2_out_requests_xmt_dv_s1 <= internal_clock_2_out_requests_xmt_dv_s1;

end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity nios_system_reset_clk_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity nios_system_reset_clk_domain_synch_module;


architecture europa of nios_system_reset_clk_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity nios_system_reset_rcv_clk_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity nios_system_reset_rcv_clk_domain_synch_module;


architecture europa of nios_system_reset_rcv_clk_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity nios_system_reset_xmt_clk_domain_synch_module is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal data_in : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal data_out : OUT STD_LOGIC
              );
end entity nios_system_reset_xmt_clk_domain_synch_module;


architecture europa of nios_system_reset_xmt_clk_domain_synch_module is
                signal data_in_d1 :  STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of data_in_d1 : signal is "MAX_DELAY=100ns ; PRESERVE_REGISTER=ON";
attribute ALTERA_ATTRIBUTE of data_out : signal is "PRESERVE_REGISTER=ON";

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_in_d1 <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_in_d1 <= data_in;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      data_out <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        data_out <= data_in_d1;
      end if;
    end if;

  end process;


end europa;



-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity nios_system is 
        port (
              -- 1) global signals:
                 signal clk : IN STD_LOGIC;
                 signal rcv_clk : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal xmt_clk : IN STD_LOGIC;

              -- the_dm9000a_0
                 signal ENET_CLK_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal ENET_CMD_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal ENET_CS_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal ENET_DATA_to_and_from_the_dm9000a_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal ENET_INT_to_the_dm9000a_0 : IN STD_LOGIC;
                 signal ENET_RD_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal ENET_RST_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal ENET_WR_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                 signal iOSC_50_to_the_dm9000a_0 : IN STD_LOGIC;

              -- the_lcd_16207_0
                 signal LCD_E_from_the_lcd_16207_0 : OUT STD_LOGIC;
                 signal LCD_RS_from_the_lcd_16207_0 : OUT STD_LOGIC;
                 signal LCD_RW_from_the_lcd_16207_0 : OUT STD_LOGIC;
                 signal LCD_data_to_and_from_the_lcd_16207_0 : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

              -- the_rcv_data
                 signal in_port_to_the_rcv_data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

              -- the_rcv_dv
                 signal in_port_to_the_rcv_dv : IN STD_LOGIC;

              -- the_xmt_data
                 signal out_port_from_the_xmt_data : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

              -- the_xmt_dv
                 signal out_port_from_the_xmt_dv : OUT STD_LOGIC
              );
end entity nios_system;


architecture europa of nios_system is
component clock_0_in_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_0_in_endofpacket : IN STD_LOGIC;
                    signal clock_0_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_0_in_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_0_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_0_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_in_read : OUT STD_LOGIC;
                    signal clock_0_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_0_in_reset_n : OUT STD_LOGIC;
                    signal clock_0_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_0_in_write : OUT STD_LOGIC;
                    signal clock_0_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal cpu_0_data_master_granted_clock_0_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_0_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_0_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_0_in : OUT STD_LOGIC;
                    signal d1_clock_0_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_0_in_arbitrator;

component clock_0_out_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_0_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_out_granted_rcv_dv_s1 : IN STD_LOGIC;
                    signal clock_0_out_qualified_request_rcv_dv_s1 : IN STD_LOGIC;
                    signal clock_0_out_read : IN STD_LOGIC;
                    signal clock_0_out_read_data_valid_rcv_dv_s1 : IN STD_LOGIC;
                    signal clock_0_out_requests_rcv_dv_s1 : IN STD_LOGIC;
                    signal clock_0_out_write : IN STD_LOGIC;
                    signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal d1_rcv_dv_s1_end_xfer : IN STD_LOGIC;
                    signal rcv_dv_s1_readdata_from_sa : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_0_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_0_out_reset_n : OUT STD_LOGIC;
                    signal clock_0_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_0_out_arbitrator;

component clock_0 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_0;

component clock_1_in_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_1_in_endofpacket : IN STD_LOGIC;
                    signal clock_1_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_1_in_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_1_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_1_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_in_read : OUT STD_LOGIC;
                    signal clock_1_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_1_in_reset_n : OUT STD_LOGIC;
                    signal clock_1_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_1_in_write : OUT STD_LOGIC;
                    signal clock_1_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal cpu_0_data_master_granted_clock_1_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_1_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_1_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_1_in : OUT STD_LOGIC;
                    signal d1_clock_1_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_1_in_arbitrator;

component clock_1_out_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_1_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_out_granted_rcv_data_s1 : IN STD_LOGIC;
                    signal clock_1_out_qualified_request_rcv_data_s1 : IN STD_LOGIC;
                    signal clock_1_out_read : IN STD_LOGIC;
                    signal clock_1_out_read_data_valid_rcv_data_s1 : IN STD_LOGIC;
                    signal clock_1_out_requests_rcv_data_s1 : IN STD_LOGIC;
                    signal clock_1_out_write : IN STD_LOGIC;
                    signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal d1_rcv_data_s1_end_xfer : IN STD_LOGIC;
                    signal rcv_data_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_1_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_1_out_reset_n : OUT STD_LOGIC;
                    signal clock_1_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_1_out_arbitrator;

component clock_1 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_1;

component clock_2_in_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_2_in_endofpacket : IN STD_LOGIC;
                    signal clock_2_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_2_in_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_2_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_2_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_in_read : OUT STD_LOGIC;
                    signal clock_2_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_2_in_reset_n : OUT STD_LOGIC;
                    signal clock_2_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_2_in_write : OUT STD_LOGIC;
                    signal clock_2_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal cpu_0_data_master_granted_clock_2_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_2_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_2_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_2_in : OUT STD_LOGIC;
                    signal d1_clock_2_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_2_in_arbitrator;

component clock_2_out_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_2_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_out_granted_xmt_dv_s1 : IN STD_LOGIC;
                    signal clock_2_out_qualified_request_xmt_dv_s1 : IN STD_LOGIC;
                    signal clock_2_out_read : IN STD_LOGIC;
                    signal clock_2_out_read_data_valid_xmt_dv_s1 : IN STD_LOGIC;
                    signal clock_2_out_requests_xmt_dv_s1 : IN STD_LOGIC;
                    signal clock_2_out_write : IN STD_LOGIC;
                    signal clock_2_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal d1_xmt_dv_s1_end_xfer : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_2_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_2_out_reset_n : OUT STD_LOGIC;
                    signal clock_2_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_2_out_arbitrator;

component clock_2 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_2;

component clock_3_in_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_3_in_endofpacket : IN STD_LOGIC;
                    signal clock_3_in_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_3_in_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_3_in_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_in_endofpacket_from_sa : OUT STD_LOGIC;
                    signal clock_3_in_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_in_read : OUT STD_LOGIC;
                    signal clock_3_in_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_3_in_reset_n : OUT STD_LOGIC;
                    signal clock_3_in_waitrequest_from_sa : OUT STD_LOGIC;
                    signal clock_3_in_write : OUT STD_LOGIC;
                    signal clock_3_in_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal cpu_0_data_master_granted_clock_3_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_3_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_3_in : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_3_in : OUT STD_LOGIC;
                    signal d1_clock_3_in_end_xfer : OUT STD_LOGIC
                 );
end component clock_3_in_arbitrator;

component clock_3_out_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_3_out_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_out_granted_xmt_data_s1 : IN STD_LOGIC;
                    signal clock_3_out_qualified_request_xmt_data_s1 : IN STD_LOGIC;
                    signal clock_3_out_read : IN STD_LOGIC;
                    signal clock_3_out_read_data_valid_xmt_data_s1 : IN STD_LOGIC;
                    signal clock_3_out_requests_xmt_data_s1 : IN STD_LOGIC;
                    signal clock_3_out_write : IN STD_LOGIC;
                    signal clock_3_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal d1_xmt_data_s1_end_xfer : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_3_out_address_to_slave : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_out_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_3_out_reset_n : OUT STD_LOGIC;
                    signal clock_3_out_waitrequest : OUT STD_LOGIC
                 );
end component clock_3_out_arbitrator;

component clock_3 is 
           port (
                 -- inputs:
                    signal master_clk : IN STD_LOGIC;
                    signal master_endofpacket : IN STD_LOGIC;
                    signal master_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal master_reset_n : IN STD_LOGIC;
                    signal master_waitrequest : IN STD_LOGIC;
                    signal slave_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_clk : IN STD_LOGIC;
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal slave_read : IN STD_LOGIC;
                    signal slave_reset_n : IN STD_LOGIC;
                    signal slave_write : IN STD_LOGIC;
                    signal slave_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal master_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal master_read : OUT STD_LOGIC;
                    signal master_write : OUT STD_LOGIC;
                    signal master_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_endofpacket : OUT STD_LOGIC;
                    signal slave_readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal slave_waitrequest : OUT STD_LOGIC
                 );
end component clock_3;

component cpu_0_jtag_debug_module_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_debugaccess : IN STD_LOGIC;
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_instruction_master_latency_counter : IN STD_LOGIC;
                    signal cpu_0_instruction_master_read : IN STD_LOGIC;
                    signal cpu_0_jtag_debug_module_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_jtag_debug_module_resetrequest : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_granted_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_granted_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_requests_cpu_0_jtag_debug_module : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                    signal cpu_0_jtag_debug_module_begintransfer : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_jtag_debug_module_chipselect : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_debugaccess : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_jtag_debug_module_reset : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_resetrequest_from_sa : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_write : OUT STD_LOGIC;
                    signal cpu_0_jtag_debug_module_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_cpu_0_jtag_debug_module_end_xfer : OUT STD_LOGIC
                 );
end component cpu_0_jtag_debug_module_arbitrator;

component cpu_0_custom_instruction_master_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal endian_cpu_0_s1_result_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_custom_instruction_master_combo_result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_custom_instruction_master_reset_n : OUT STD_LOGIC;
                    signal endian_cpu_0_s1_select : OUT STD_LOGIC
                 );
end component cpu_0_custom_instruction_master_arbitrator;

component cpu_0_data_master_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_0_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_0_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal clock_1_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_1_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal clock_2_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_2_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal clock_3_in_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal clock_3_in_waitrequest_from_sa : IN STD_LOGIC;
                    signal cpu_0_data_master_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_debugaccess : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_clock_0_in : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_clock_1_in : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_clock_2_in : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_clock_3_in : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_lcd_16207_0_control_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_granted_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_0_in : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_1_in : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_2_in : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_clock_3_in : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_lcd_16207_0_control_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_0_in : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_1_in : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_2_in : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_clock_3_in : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_0_in : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_1_in : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_2_in : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_clock_3_in : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_lcd_16207_0_control_slave : IN STD_LOGIC;
                    signal cpu_0_data_master_requests_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_clock_0_in_end_xfer : IN STD_LOGIC;
                    signal d1_clock_1_in_end_xfer : IN STD_LOGIC;
                    signal d1_clock_2_in_end_xfer : IN STD_LOGIC;
                    signal d1_clock_3_in_end_xfer : IN STD_LOGIC;
                    signal d1_cpu_0_jtag_debug_module_end_xfer : IN STD_LOGIC;
                    signal d1_dm9000a_0_avalon_slave_0_end_xfer : IN STD_LOGIC;
                    signal d1_jtag_uart_0_avalon_jtag_slave_end_xfer : IN STD_LOGIC;
                    signal d1_lcd_16207_0_control_slave_end_xfer : IN STD_LOGIC;
                    signal d1_onchip_memory_0_s1_end_xfer : IN STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_irq_from_sa : IN STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_readdata_from_sa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal jtag_uart_0_avalon_jtag_slave_irq_from_sa : IN STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa : IN STD_LOGIC;
                    signal lcd_16207_0_control_slave_readdata_from_sa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal lcd_16207_0_control_slave_wait_counter_eq_0 : IN STD_LOGIC;
                    signal lcd_16207_0_control_slave_wait_counter_eq_1 : IN STD_LOGIC;
                    signal onchip_memory_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_irq : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_data_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_data_master_waitrequest : OUT STD_LOGIC
                 );
end component cpu_0_data_master_arbitrator;

component cpu_0_instruction_master_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_instruction_master_address : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_instruction_master_granted_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_instruction_master_granted_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_instruction_master_read : IN STD_LOGIC;
                    signal cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_instruction_master_requests_cpu_0_jtag_debug_module : IN STD_LOGIC;
                    signal cpu_0_instruction_master_requests_onchip_memory_0_s1 : IN STD_LOGIC;
                    signal cpu_0_jtag_debug_module_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d1_cpu_0_jtag_debug_module_end_xfer : IN STD_LOGIC;
                    signal d1_onchip_memory_0_s1_end_xfer : IN STD_LOGIC;
                    signal onchip_memory_0_s1_readdata_from_sa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_instruction_master_address_to_slave : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_instruction_master_latency_counter : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_instruction_master_readdatavalid : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_waitrequest : OUT STD_LOGIC
                 );
end component cpu_0_instruction_master_arbitrator;

component cpu_0 is 
           port (
                 -- inputs:
                    signal E_ci_combo_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal d_irq : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal d_waitrequest : IN STD_LOGIC;
                    signal i_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal i_readdatavalid : IN STD_LOGIC;
                    signal i_waitrequest : IN STD_LOGIC;
                    signal jtag_debug_module_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
                    signal jtag_debug_module_begintransfer : IN STD_LOGIC;
                    signal jtag_debug_module_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal jtag_debug_module_clk : IN STD_LOGIC;
                    signal jtag_debug_module_debugaccess : IN STD_LOGIC;
                    signal jtag_debug_module_reset : IN STD_LOGIC;
                    signal jtag_debug_module_select : IN STD_LOGIC;
                    signal jtag_debug_module_write : IN STD_LOGIC;
                    signal jtag_debug_module_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal E_ci_combo_a : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
                    signal E_ci_combo_b : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
                    signal E_ci_combo_c : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
                    signal E_ci_combo_dataa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal E_ci_combo_datab : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal E_ci_combo_estatus : OUT STD_LOGIC;
                    signal E_ci_combo_ipending : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal E_ci_combo_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal E_ci_combo_readra : OUT STD_LOGIC;
                    signal E_ci_combo_readrb : OUT STD_LOGIC;
                    signal E_ci_combo_status : OUT STD_LOGIC;
                    signal E_ci_combo_writerc : OUT STD_LOGIC;
                    signal d_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal d_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal d_read : OUT STD_LOGIC;
                    signal d_write : OUT STD_LOGIC;
                    signal d_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal i_address : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal i_read : OUT STD_LOGIC;
                    signal jtag_debug_module_debugaccess_to_roms : OUT STD_LOGIC;
                    signal jtag_debug_module_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_debug_module_resetrequest : OUT STD_LOGIC
                 );
end component cpu_0;

component dm9000a_0_avalon_slave_0_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal dm9000a_0_avalon_slave_0_irq : IN STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 : OUT STD_LOGIC;
                    signal d1_dm9000a_0_avalon_slave_0_end_xfer : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_address : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_chipselect_n : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_irq_from_sa : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_read_n : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_readdata_from_sa : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal dm9000a_0_avalon_slave_0_reset_n : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_write_n : OUT STD_LOGIC;
                    signal dm9000a_0_avalon_slave_0_writedata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component dm9000a_0_avalon_slave_0_arbitrator;

component dm9000a_0 is 
           port (
                 -- inputs:
                    signal ENET_INT : IN STD_LOGIC;
                    signal iCLK : IN STD_LOGIC;
                    signal iCMD : IN STD_LOGIC;
                    signal iCS_N : IN STD_LOGIC;
                    signal iDATA : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal iOSC_50 : IN STD_LOGIC;
                    signal iRD_N : IN STD_LOGIC;
                    signal iRST_N : IN STD_LOGIC;
                    signal iWR_N : IN STD_LOGIC;

                 -- outputs:
                    signal ENET_CLK : OUT STD_LOGIC;
                    signal ENET_CMD : OUT STD_LOGIC;
                    signal ENET_CS_N : OUT STD_LOGIC;
                    signal ENET_DATA : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal ENET_RD_N : OUT STD_LOGIC;
                    signal ENET_RST_N : OUT STD_LOGIC;
                    signal ENET_WR_N : OUT STD_LOGIC;
                    signal oDATA : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal oINT : OUT STD_LOGIC
                 );
end component dm9000a_0;

component endian_cpu_0_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_custom_instruction_master_combo_dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_custom_instruction_master_combo_datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal endian_cpu_0_s1_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal endian_cpu_0_s1_select : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal endian_cpu_0_s1_dataa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal endian_cpu_0_s1_datab : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal endian_cpu_0_s1_result_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component endian_cpu_0_s1_arbitrator;

component endian_cpu_0 is 
           port (
                 -- inputs:
                    signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- outputs:
                    signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component endian_cpu_0;

component jtag_uart_0_avalon_jtag_slave_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_uart_0_avalon_jtag_slave_dataavailable : IN STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_irq : IN STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_uart_0_avalon_jtag_slave_readyfordata : IN STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_waitrequest : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave : OUT STD_LOGIC;
                    signal d1_jtag_uart_0_avalon_jtag_slave_end_xfer : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_address : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_chipselect : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_irq_from_sa : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_read_n : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_reset_n : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_write_n : OUT STD_LOGIC;
                    signal jtag_uart_0_avalon_jtag_slave_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component jtag_uart_0_avalon_jtag_slave_arbitrator;

component jtag_uart_0 is 
           port (
                 -- inputs:
                    signal av_address : IN STD_LOGIC;
                    signal av_chipselect : IN STD_LOGIC;
                    signal av_read_n : IN STD_LOGIC;
                    signal av_write_n : IN STD_LOGIC;
                    signal av_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal rst_n : IN STD_LOGIC;

                 -- outputs:
                    signal av_irq : OUT STD_LOGIC;
                    signal av_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal av_waitrequest : OUT STD_LOGIC;
                    signal dataavailable : OUT STD_LOGIC;
                    signal readyfordata : OUT STD_LOGIC
                 );
end component jtag_uart_0;

component lcd_16207_0_control_slave_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal lcd_16207_0_control_slave_readdata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_granted_lcd_16207_0_control_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_lcd_16207_0_control_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_lcd_16207_0_control_slave : OUT STD_LOGIC;
                    signal d1_lcd_16207_0_control_slave_end_xfer : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal lcd_16207_0_control_slave_begintransfer : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_read : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_readdata_from_sa : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal lcd_16207_0_control_slave_wait_counter_eq_0 : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_wait_counter_eq_1 : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_write : OUT STD_LOGIC;
                    signal lcd_16207_0_control_slave_writedata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component lcd_16207_0_control_slave_arbitrator;

component lcd_16207_0 is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal LCD_E : OUT STD_LOGIC;
                    signal LCD_RS : OUT STD_LOGIC;
                    signal LCD_RW : OUT STD_LOGIC;
                    signal LCD_data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component lcd_16207_0;

component onchip_memory_0_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal cpu_0_data_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal cpu_0_data_master_read : IN STD_LOGIC;
                    signal cpu_0_data_master_waitrequest : IN STD_LOGIC;
                    signal cpu_0_data_master_write : IN STD_LOGIC;
                    signal cpu_0_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal cpu_0_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                    signal cpu_0_instruction_master_latency_counter : IN STD_LOGIC;
                    signal cpu_0_instruction_master_read : IN STD_LOGIC;
                    signal onchip_memory_0_s1_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal cpu_0_data_master_granted_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_data_master_qualified_request_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_data_master_requests_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_granted_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal cpu_0_instruction_master_requests_onchip_memory_0_s1 : OUT STD_LOGIC;
                    signal d1_onchip_memory_0_s1_end_xfer : OUT STD_LOGIC;
                    signal onchip_memory_0_s1_address : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal onchip_memory_0_s1_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal onchip_memory_0_s1_chipselect : OUT STD_LOGIC;
                    signal onchip_memory_0_s1_clken : OUT STD_LOGIC;
                    signal onchip_memory_0_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal onchip_memory_0_s1_write : OUT STD_LOGIC;
                    signal onchip_memory_0_s1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 : OUT STD_LOGIC
                 );
end component onchip_memory_0_s1_arbitrator;

component onchip_memory_0 is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                    signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clken : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

                 -- outputs:
                    signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component onchip_memory_0;

component rcv_data_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_1_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_1_out_read : IN STD_LOGIC;
                    signal clock_1_out_write : IN STD_LOGIC;
                    signal clock_1_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rcv_data_s1_readdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_1_out_granted_rcv_data_s1 : OUT STD_LOGIC;
                    signal clock_1_out_qualified_request_rcv_data_s1 : OUT STD_LOGIC;
                    signal clock_1_out_read_data_valid_rcv_data_s1 : OUT STD_LOGIC;
                    signal clock_1_out_requests_rcv_data_s1 : OUT STD_LOGIC;
                    signal d1_rcv_data_s1_end_xfer : OUT STD_LOGIC;
                    signal rcv_data_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal rcv_data_s1_chipselect : OUT STD_LOGIC;
                    signal rcv_data_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal rcv_data_s1_reset_n : OUT STD_LOGIC;
                    signal rcv_data_s1_write_n : OUT STD_LOGIC;
                    signal rcv_data_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component rcv_data_s1_arbitrator;

component rcv_data is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal in_port : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- outputs:
                    signal readdata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component rcv_data;

component rcv_dv_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_0_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_0_out_read : IN STD_LOGIC;
                    signal clock_0_out_write : IN STD_LOGIC;
                    signal clock_0_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rcv_dv_s1_readdata : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_0_out_granted_rcv_dv_s1 : OUT STD_LOGIC;
                    signal clock_0_out_qualified_request_rcv_dv_s1 : OUT STD_LOGIC;
                    signal clock_0_out_read_data_valid_rcv_dv_s1 : OUT STD_LOGIC;
                    signal clock_0_out_requests_rcv_dv_s1 : OUT STD_LOGIC;
                    signal d1_rcv_dv_s1_end_xfer : OUT STD_LOGIC;
                    signal rcv_dv_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal rcv_dv_s1_chipselect : OUT STD_LOGIC;
                    signal rcv_dv_s1_readdata_from_sa : OUT STD_LOGIC;
                    signal rcv_dv_s1_reset_n : OUT STD_LOGIC;
                    signal rcv_dv_s1_write_n : OUT STD_LOGIC;
                    signal rcv_dv_s1_writedata : OUT STD_LOGIC
                 );
end component rcv_dv_s1_arbitrator;

component rcv_dv is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal in_port : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC;

                 -- outputs:
                    signal readdata : OUT STD_LOGIC
                 );
end component rcv_dv;

component xmt_data_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_3_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_3_out_read : IN STD_LOGIC;
                    signal clock_3_out_write : IN STD_LOGIC;
                    signal clock_3_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_3_out_granted_xmt_data_s1 : OUT STD_LOGIC;
                    signal clock_3_out_qualified_request_xmt_data_s1 : OUT STD_LOGIC;
                    signal clock_3_out_read_data_valid_xmt_data_s1 : OUT STD_LOGIC;
                    signal clock_3_out_requests_xmt_data_s1 : OUT STD_LOGIC;
                    signal d1_xmt_data_s1_end_xfer : OUT STD_LOGIC;
                    signal xmt_data_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal xmt_data_s1_chipselect : OUT STD_LOGIC;
                    signal xmt_data_s1_reset_n : OUT STD_LOGIC;
                    signal xmt_data_s1_write_n : OUT STD_LOGIC;
                    signal xmt_data_s1_writedata : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component xmt_data_s1_arbitrator;

component xmt_data is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- outputs:
                    signal out_port : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
                 );
end component xmt_data;

component xmt_dv_s1_arbitrator is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clock_2_out_address_to_slave : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_out_nativeaddress : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clock_2_out_read : IN STD_LOGIC;
                    signal clock_2_out_write : IN STD_LOGIC;
                    signal clock_2_out_writedata : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal clock_2_out_granted_xmt_dv_s1 : OUT STD_LOGIC;
                    signal clock_2_out_qualified_request_xmt_dv_s1 : OUT STD_LOGIC;
                    signal clock_2_out_read_data_valid_xmt_dv_s1 : OUT STD_LOGIC;
                    signal clock_2_out_requests_xmt_dv_s1 : OUT STD_LOGIC;
                    signal d1_xmt_dv_s1_end_xfer : OUT STD_LOGIC;
                    signal xmt_dv_s1_address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal xmt_dv_s1_chipselect : OUT STD_LOGIC;
                    signal xmt_dv_s1_reset_n : OUT STD_LOGIC;
                    signal xmt_dv_s1_write_n : OUT STD_LOGIC;
                    signal xmt_dv_s1_writedata : OUT STD_LOGIC
                 );
end component xmt_dv_s1_arbitrator;

component xmt_dv is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC;

                 -- outputs:
                    signal out_port : OUT STD_LOGIC
                 );
end component xmt_dv;

component nios_system_reset_clk_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component nios_system_reset_clk_domain_synch_module;

component nios_system_reset_rcv_clk_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component nios_system_reset_rcv_clk_domain_synch_module;

component nios_system_reset_xmt_clk_domain_synch_module is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal data_in : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal data_out : OUT STD_LOGIC
                 );
end component nios_system_reset_xmt_clk_domain_synch_module;

                signal clk_reset_n :  STD_LOGIC;
                signal clock_0_in_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_in_endofpacket :  STD_LOGIC;
                signal clock_0_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_0_in_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_in_read :  STD_LOGIC;
                signal clock_0_in_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_0_in_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_0_in_reset_n :  STD_LOGIC;
                signal clock_0_in_waitrequest :  STD_LOGIC;
                signal clock_0_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_0_in_write :  STD_LOGIC;
                signal clock_0_in_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_0_out_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_out_endofpacket :  STD_LOGIC;
                signal clock_0_out_granted_rcv_dv_s1 :  STD_LOGIC;
                signal clock_0_out_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_0_out_qualified_request_rcv_dv_s1 :  STD_LOGIC;
                signal clock_0_out_read :  STD_LOGIC;
                signal clock_0_out_read_data_valid_rcv_dv_s1 :  STD_LOGIC;
                signal clock_0_out_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_0_out_requests_rcv_dv_s1 :  STD_LOGIC;
                signal clock_0_out_reset_n :  STD_LOGIC;
                signal clock_0_out_waitrequest :  STD_LOGIC;
                signal clock_0_out_write :  STD_LOGIC;
                signal clock_0_out_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_1_in_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_endofpacket :  STD_LOGIC;
                signal clock_1_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_1_in_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_in_read :  STD_LOGIC;
                signal clock_1_in_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_1_in_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_1_in_reset_n :  STD_LOGIC;
                signal clock_1_in_waitrequest :  STD_LOGIC;
                signal clock_1_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_1_in_write :  STD_LOGIC;
                signal clock_1_in_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_1_out_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_endofpacket :  STD_LOGIC;
                signal clock_1_out_granted_rcv_data_s1 :  STD_LOGIC;
                signal clock_1_out_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_1_out_qualified_request_rcv_data_s1 :  STD_LOGIC;
                signal clock_1_out_read :  STD_LOGIC;
                signal clock_1_out_read_data_valid_rcv_data_s1 :  STD_LOGIC;
                signal clock_1_out_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_1_out_requests_rcv_data_s1 :  STD_LOGIC;
                signal clock_1_out_reset_n :  STD_LOGIC;
                signal clock_1_out_waitrequest :  STD_LOGIC;
                signal clock_1_out_write :  STD_LOGIC;
                signal clock_1_out_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_2_in_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_in_endofpacket :  STD_LOGIC;
                signal clock_2_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_2_in_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_in_read :  STD_LOGIC;
                signal clock_2_in_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_2_in_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_2_in_reset_n :  STD_LOGIC;
                signal clock_2_in_waitrequest :  STD_LOGIC;
                signal clock_2_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_2_in_write :  STD_LOGIC;
                signal clock_2_in_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_2_out_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_out_endofpacket :  STD_LOGIC;
                signal clock_2_out_granted_xmt_dv_s1 :  STD_LOGIC;
                signal clock_2_out_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_2_out_qualified_request_xmt_dv_s1 :  STD_LOGIC;
                signal clock_2_out_read :  STD_LOGIC;
                signal clock_2_out_read_data_valid_xmt_dv_s1 :  STD_LOGIC;
                signal clock_2_out_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_2_out_requests_xmt_dv_s1 :  STD_LOGIC;
                signal clock_2_out_reset_n :  STD_LOGIC;
                signal clock_2_out_waitrequest :  STD_LOGIC;
                signal clock_2_out_write :  STD_LOGIC;
                signal clock_2_out_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_3_in_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_in_endofpacket :  STD_LOGIC;
                signal clock_3_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_3_in_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_in_read :  STD_LOGIC;
                signal clock_3_in_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_3_in_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_3_in_reset_n :  STD_LOGIC;
                signal clock_3_in_waitrequest :  STD_LOGIC;
                signal clock_3_in_waitrequest_from_sa :  STD_LOGIC;
                signal clock_3_in_write :  STD_LOGIC;
                signal clock_3_in_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_3_out_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_out_address_to_slave :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_out_endofpacket :  STD_LOGIC;
                signal clock_3_out_granted_xmt_data_s1 :  STD_LOGIC;
                signal clock_3_out_nativeaddress :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal clock_3_out_qualified_request_xmt_data_s1 :  STD_LOGIC;
                signal clock_3_out_read :  STD_LOGIC;
                signal clock_3_out_read_data_valid_xmt_data_s1 :  STD_LOGIC;
                signal clock_3_out_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clock_3_out_requests_xmt_data_s1 :  STD_LOGIC;
                signal clock_3_out_reset_n :  STD_LOGIC;
                signal clock_3_out_waitrequest :  STD_LOGIC;
                signal clock_3_out_write :  STD_LOGIC;
                signal clock_3_out_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_a :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_b :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_c :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_dataa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_datab :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_estatus :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_ipending :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_n :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_readra :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_readrb :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_status :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_writerc :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_reset_n :  STD_LOGIC;
                signal cpu_0_data_master_address :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal cpu_0_data_master_address_to_slave :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal cpu_0_data_master_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal cpu_0_data_master_debugaccess :  STD_LOGIC;
                signal cpu_0_data_master_granted_clock_0_in :  STD_LOGIC;
                signal cpu_0_data_master_granted_clock_1_in :  STD_LOGIC;
                signal cpu_0_data_master_granted_clock_2_in :  STD_LOGIC;
                signal cpu_0_data_master_granted_clock_3_in :  STD_LOGIC;
                signal cpu_0_data_master_granted_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal cpu_0_data_master_granted_lcd_16207_0_control_slave :  STD_LOGIC;
                signal cpu_0_data_master_granted_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_data_master_irq :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_data_master_qualified_request_clock_0_in :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_clock_1_in :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_clock_2_in :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_clock_3_in :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_lcd_16207_0_control_slave :  STD_LOGIC;
                signal cpu_0_data_master_qualified_request_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_data_master_read :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_clock_0_in :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_clock_1_in :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_clock_2_in :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_clock_3_in :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave :  STD_LOGIC;
                signal cpu_0_data_master_read_data_valid_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_data_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_data_master_requests_clock_0_in :  STD_LOGIC;
                signal cpu_0_data_master_requests_clock_1_in :  STD_LOGIC;
                signal cpu_0_data_master_requests_clock_2_in :  STD_LOGIC;
                signal cpu_0_data_master_requests_clock_3_in :  STD_LOGIC;
                signal cpu_0_data_master_requests_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 :  STD_LOGIC;
                signal cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave :  STD_LOGIC;
                signal cpu_0_data_master_requests_lcd_16207_0_control_slave :  STD_LOGIC;
                signal cpu_0_data_master_requests_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_data_master_waitrequest :  STD_LOGIC;
                signal cpu_0_data_master_write :  STD_LOGIC;
                signal cpu_0_data_master_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_instruction_master_address :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal cpu_0_instruction_master_address_to_slave :  STD_LOGIC_VECTOR (17 DOWNTO 0);
                signal cpu_0_instruction_master_granted_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_instruction_master_granted_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_instruction_master_latency_counter :  STD_LOGIC;
                signal cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_instruction_master_read :  STD_LOGIC;
                signal cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_instruction_master_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_instruction_master_readdatavalid :  STD_LOGIC;
                signal cpu_0_instruction_master_requests_cpu_0_jtag_debug_module :  STD_LOGIC;
                signal cpu_0_instruction_master_requests_onchip_memory_0_s1 :  STD_LOGIC;
                signal cpu_0_instruction_master_waitrequest :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_address :  STD_LOGIC_VECTOR (8 DOWNTO 0);
                signal cpu_0_jtag_debug_module_begintransfer :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal cpu_0_jtag_debug_module_chipselect :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_debugaccess :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_jtag_debug_module_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_jtag_debug_module_reset :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_resetrequest :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_resetrequest_from_sa :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_write :  STD_LOGIC;
                signal cpu_0_jtag_debug_module_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal d1_clock_0_in_end_xfer :  STD_LOGIC;
                signal d1_clock_1_in_end_xfer :  STD_LOGIC;
                signal d1_clock_2_in_end_xfer :  STD_LOGIC;
                signal d1_clock_3_in_end_xfer :  STD_LOGIC;
                signal d1_cpu_0_jtag_debug_module_end_xfer :  STD_LOGIC;
                signal d1_dm9000a_0_avalon_slave_0_end_xfer :  STD_LOGIC;
                signal d1_jtag_uart_0_avalon_jtag_slave_end_xfer :  STD_LOGIC;
                signal d1_lcd_16207_0_control_slave_end_xfer :  STD_LOGIC;
                signal d1_onchip_memory_0_s1_end_xfer :  STD_LOGIC;
                signal d1_rcv_data_s1_end_xfer :  STD_LOGIC;
                signal d1_rcv_dv_s1_end_xfer :  STD_LOGIC;
                signal d1_xmt_data_s1_end_xfer :  STD_LOGIC;
                signal d1_xmt_dv_s1_end_xfer :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_address :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_chipselect_n :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_irq :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_irq_from_sa :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_read_n :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dm9000a_0_avalon_slave_0_readdata_from_sa :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal dm9000a_0_avalon_slave_0_reset_n :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_write_n :  STD_LOGIC;
                signal dm9000a_0_avalon_slave_0_writedata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal endian_cpu_0_s1_dataa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal endian_cpu_0_s1_datab :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal endian_cpu_0_s1_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal endian_cpu_0_s1_result_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal endian_cpu_0_s1_select :  STD_LOGIC;
                signal internal_ENET_CLK_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_ENET_CMD_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_ENET_CS_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_ENET_RD_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_ENET_RST_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_ENET_WR_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal internal_LCD_E_from_the_lcd_16207_0 :  STD_LOGIC;
                signal internal_LCD_RS_from_the_lcd_16207_0 :  STD_LOGIC;
                signal internal_LCD_RW_from_the_lcd_16207_0 :  STD_LOGIC;
                signal internal_out_port_from_the_xmt_data :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal internal_out_port_from_the_xmt_dv :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_address :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_chipselect :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_dataavailable :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_irq :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_irq_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_read_n :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal jtag_uart_0_avalon_jtag_slave_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal jtag_uart_0_avalon_jtag_slave_readyfordata :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_reset_n :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_waitrequest :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_write_n :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal lcd_16207_0_control_slave_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal lcd_16207_0_control_slave_begintransfer :  STD_LOGIC;
                signal lcd_16207_0_control_slave_irq :  STD_LOGIC;
                signal lcd_16207_0_control_slave_read :  STD_LOGIC;
                signal lcd_16207_0_control_slave_readdata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal lcd_16207_0_control_slave_readdata_from_sa :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal lcd_16207_0_control_slave_wait_counter_eq_0 :  STD_LOGIC;
                signal lcd_16207_0_control_slave_wait_counter_eq_1 :  STD_LOGIC;
                signal lcd_16207_0_control_slave_write :  STD_LOGIC;
                signal lcd_16207_0_control_slave_writedata :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal module_input :  STD_LOGIC;
                signal module_input1 :  STD_LOGIC;
                signal module_input2 :  STD_LOGIC;
                signal onchip_memory_0_s1_address :  STD_LOGIC_VECTOR (12 DOWNTO 0);
                signal onchip_memory_0_s1_byteenable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal onchip_memory_0_s1_chipselect :  STD_LOGIC;
                signal onchip_memory_0_s1_clken :  STD_LOGIC;
                signal onchip_memory_0_s1_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal onchip_memory_0_s1_readdata_from_sa :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal onchip_memory_0_s1_write :  STD_LOGIC;
                signal onchip_memory_0_s1_writedata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal rcv_clk_reset_n :  STD_LOGIC;
                signal rcv_data_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal rcv_data_s1_chipselect :  STD_LOGIC;
                signal rcv_data_s1_readdata :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal rcv_data_s1_readdata_from_sa :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal rcv_data_s1_reset_n :  STD_LOGIC;
                signal rcv_data_s1_write_n :  STD_LOGIC;
                signal rcv_data_s1_writedata :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal rcv_dv_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal rcv_dv_s1_chipselect :  STD_LOGIC;
                signal rcv_dv_s1_readdata :  STD_LOGIC;
                signal rcv_dv_s1_readdata_from_sa :  STD_LOGIC;
                signal rcv_dv_s1_reset_n :  STD_LOGIC;
                signal rcv_dv_s1_write_n :  STD_LOGIC;
                signal rcv_dv_s1_writedata :  STD_LOGIC;
                signal registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 :  STD_LOGIC;
                signal reset_n_sources :  STD_LOGIC;
                signal xmt_clk_reset_n :  STD_LOGIC;
                signal xmt_data_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal xmt_data_s1_chipselect :  STD_LOGIC;
                signal xmt_data_s1_reset_n :  STD_LOGIC;
                signal xmt_data_s1_write_n :  STD_LOGIC;
                signal xmt_data_s1_writedata :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal xmt_dv_s1_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal xmt_dv_s1_chipselect :  STD_LOGIC;
                signal xmt_dv_s1_reset_n :  STD_LOGIC;
                signal xmt_dv_s1_write_n :  STD_LOGIC;
                signal xmt_dv_s1_writedata :  STD_LOGIC;

begin

  --the_clock_0_in, which is an e_instance
  the_clock_0_in : clock_0_in_arbitrator
    port map(
      clock_0_in_address => clock_0_in_address,
      clock_0_in_endofpacket_from_sa => clock_0_in_endofpacket_from_sa,
      clock_0_in_nativeaddress => clock_0_in_nativeaddress,
      clock_0_in_read => clock_0_in_read,
      clock_0_in_readdata_from_sa => clock_0_in_readdata_from_sa,
      clock_0_in_reset_n => clock_0_in_reset_n,
      clock_0_in_waitrequest_from_sa => clock_0_in_waitrequest_from_sa,
      clock_0_in_write => clock_0_in_write,
      clock_0_in_writedata => clock_0_in_writedata,
      cpu_0_data_master_granted_clock_0_in => cpu_0_data_master_granted_clock_0_in,
      cpu_0_data_master_qualified_request_clock_0_in => cpu_0_data_master_qualified_request_clock_0_in,
      cpu_0_data_master_read_data_valid_clock_0_in => cpu_0_data_master_read_data_valid_clock_0_in,
      cpu_0_data_master_requests_clock_0_in => cpu_0_data_master_requests_clock_0_in,
      d1_clock_0_in_end_xfer => d1_clock_0_in_end_xfer,
      clk => clk,
      clock_0_in_endofpacket => clock_0_in_endofpacket,
      clock_0_in_readdata => clock_0_in_readdata,
      clock_0_in_waitrequest => clock_0_in_waitrequest,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      reset_n => clk_reset_n
    );


  --the_clock_0_out, which is an e_instance
  the_clock_0_out : clock_0_out_arbitrator
    port map(
      clock_0_out_address_to_slave => clock_0_out_address_to_slave,
      clock_0_out_readdata => clock_0_out_readdata,
      clock_0_out_reset_n => clock_0_out_reset_n,
      clock_0_out_waitrequest => clock_0_out_waitrequest,
      clk => rcv_clk,
      clock_0_out_address => clock_0_out_address,
      clock_0_out_granted_rcv_dv_s1 => clock_0_out_granted_rcv_dv_s1,
      clock_0_out_qualified_request_rcv_dv_s1 => clock_0_out_qualified_request_rcv_dv_s1,
      clock_0_out_read => clock_0_out_read,
      clock_0_out_read_data_valid_rcv_dv_s1 => clock_0_out_read_data_valid_rcv_dv_s1,
      clock_0_out_requests_rcv_dv_s1 => clock_0_out_requests_rcv_dv_s1,
      clock_0_out_write => clock_0_out_write,
      clock_0_out_writedata => clock_0_out_writedata,
      d1_rcv_dv_s1_end_xfer => d1_rcv_dv_s1_end_xfer,
      rcv_dv_s1_readdata_from_sa => rcv_dv_s1_readdata_from_sa,
      reset_n => rcv_clk_reset_n
    );


  --the_clock_0, which is an e_ptf_instance
  the_clock_0 : clock_0
    port map(
      master_address => clock_0_out_address,
      master_nativeaddress => clock_0_out_nativeaddress,
      master_read => clock_0_out_read,
      master_write => clock_0_out_write,
      master_writedata => clock_0_out_writedata,
      slave_endofpacket => clock_0_in_endofpacket,
      slave_readdata => clock_0_in_readdata,
      slave_waitrequest => clock_0_in_waitrequest,
      master_clk => rcv_clk,
      master_endofpacket => clock_0_out_endofpacket,
      master_readdata => clock_0_out_readdata,
      master_reset_n => clock_0_out_reset_n,
      master_waitrequest => clock_0_out_waitrequest,
      slave_address => clock_0_in_address,
      slave_clk => clk,
      slave_nativeaddress => clock_0_in_nativeaddress,
      slave_read => clock_0_in_read,
      slave_reset_n => clock_0_in_reset_n,
      slave_write => clock_0_in_write,
      slave_writedata => clock_0_in_writedata
    );


  --the_clock_1_in, which is an e_instance
  the_clock_1_in : clock_1_in_arbitrator
    port map(
      clock_1_in_address => clock_1_in_address,
      clock_1_in_endofpacket_from_sa => clock_1_in_endofpacket_from_sa,
      clock_1_in_nativeaddress => clock_1_in_nativeaddress,
      clock_1_in_read => clock_1_in_read,
      clock_1_in_readdata_from_sa => clock_1_in_readdata_from_sa,
      clock_1_in_reset_n => clock_1_in_reset_n,
      clock_1_in_waitrequest_from_sa => clock_1_in_waitrequest_from_sa,
      clock_1_in_write => clock_1_in_write,
      clock_1_in_writedata => clock_1_in_writedata,
      cpu_0_data_master_granted_clock_1_in => cpu_0_data_master_granted_clock_1_in,
      cpu_0_data_master_qualified_request_clock_1_in => cpu_0_data_master_qualified_request_clock_1_in,
      cpu_0_data_master_read_data_valid_clock_1_in => cpu_0_data_master_read_data_valid_clock_1_in,
      cpu_0_data_master_requests_clock_1_in => cpu_0_data_master_requests_clock_1_in,
      d1_clock_1_in_end_xfer => d1_clock_1_in_end_xfer,
      clk => clk,
      clock_1_in_endofpacket => clock_1_in_endofpacket,
      clock_1_in_readdata => clock_1_in_readdata,
      clock_1_in_waitrequest => clock_1_in_waitrequest,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      reset_n => clk_reset_n
    );


  --the_clock_1_out, which is an e_instance
  the_clock_1_out : clock_1_out_arbitrator
    port map(
      clock_1_out_address_to_slave => clock_1_out_address_to_slave,
      clock_1_out_readdata => clock_1_out_readdata,
      clock_1_out_reset_n => clock_1_out_reset_n,
      clock_1_out_waitrequest => clock_1_out_waitrequest,
      clk => rcv_clk,
      clock_1_out_address => clock_1_out_address,
      clock_1_out_granted_rcv_data_s1 => clock_1_out_granted_rcv_data_s1,
      clock_1_out_qualified_request_rcv_data_s1 => clock_1_out_qualified_request_rcv_data_s1,
      clock_1_out_read => clock_1_out_read,
      clock_1_out_read_data_valid_rcv_data_s1 => clock_1_out_read_data_valid_rcv_data_s1,
      clock_1_out_requests_rcv_data_s1 => clock_1_out_requests_rcv_data_s1,
      clock_1_out_write => clock_1_out_write,
      clock_1_out_writedata => clock_1_out_writedata,
      d1_rcv_data_s1_end_xfer => d1_rcv_data_s1_end_xfer,
      rcv_data_s1_readdata_from_sa => rcv_data_s1_readdata_from_sa,
      reset_n => rcv_clk_reset_n
    );


  --the_clock_1, which is an e_ptf_instance
  the_clock_1 : clock_1
    port map(
      master_address => clock_1_out_address,
      master_nativeaddress => clock_1_out_nativeaddress,
      master_read => clock_1_out_read,
      master_write => clock_1_out_write,
      master_writedata => clock_1_out_writedata,
      slave_endofpacket => clock_1_in_endofpacket,
      slave_readdata => clock_1_in_readdata,
      slave_waitrequest => clock_1_in_waitrequest,
      master_clk => rcv_clk,
      master_endofpacket => clock_1_out_endofpacket,
      master_readdata => clock_1_out_readdata,
      master_reset_n => clock_1_out_reset_n,
      master_waitrequest => clock_1_out_waitrequest,
      slave_address => clock_1_in_address,
      slave_clk => clk,
      slave_nativeaddress => clock_1_in_nativeaddress,
      slave_read => clock_1_in_read,
      slave_reset_n => clock_1_in_reset_n,
      slave_write => clock_1_in_write,
      slave_writedata => clock_1_in_writedata
    );


  --the_clock_2_in, which is an e_instance
  the_clock_2_in : clock_2_in_arbitrator
    port map(
      clock_2_in_address => clock_2_in_address,
      clock_2_in_endofpacket_from_sa => clock_2_in_endofpacket_from_sa,
      clock_2_in_nativeaddress => clock_2_in_nativeaddress,
      clock_2_in_read => clock_2_in_read,
      clock_2_in_readdata_from_sa => clock_2_in_readdata_from_sa,
      clock_2_in_reset_n => clock_2_in_reset_n,
      clock_2_in_waitrequest_from_sa => clock_2_in_waitrequest_from_sa,
      clock_2_in_write => clock_2_in_write,
      clock_2_in_writedata => clock_2_in_writedata,
      cpu_0_data_master_granted_clock_2_in => cpu_0_data_master_granted_clock_2_in,
      cpu_0_data_master_qualified_request_clock_2_in => cpu_0_data_master_qualified_request_clock_2_in,
      cpu_0_data_master_read_data_valid_clock_2_in => cpu_0_data_master_read_data_valid_clock_2_in,
      cpu_0_data_master_requests_clock_2_in => cpu_0_data_master_requests_clock_2_in,
      d1_clock_2_in_end_xfer => d1_clock_2_in_end_xfer,
      clk => clk,
      clock_2_in_endofpacket => clock_2_in_endofpacket,
      clock_2_in_readdata => clock_2_in_readdata,
      clock_2_in_waitrequest => clock_2_in_waitrequest,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      reset_n => clk_reset_n
    );


  --the_clock_2_out, which is an e_instance
  the_clock_2_out : clock_2_out_arbitrator
    port map(
      clock_2_out_address_to_slave => clock_2_out_address_to_slave,
      clock_2_out_readdata => clock_2_out_readdata,
      clock_2_out_reset_n => clock_2_out_reset_n,
      clock_2_out_waitrequest => clock_2_out_waitrequest,
      clk => xmt_clk,
      clock_2_out_address => clock_2_out_address,
      clock_2_out_granted_xmt_dv_s1 => clock_2_out_granted_xmt_dv_s1,
      clock_2_out_qualified_request_xmt_dv_s1 => clock_2_out_qualified_request_xmt_dv_s1,
      clock_2_out_read => clock_2_out_read,
      clock_2_out_read_data_valid_xmt_dv_s1 => clock_2_out_read_data_valid_xmt_dv_s1,
      clock_2_out_requests_xmt_dv_s1 => clock_2_out_requests_xmt_dv_s1,
      clock_2_out_write => clock_2_out_write,
      clock_2_out_writedata => clock_2_out_writedata,
      d1_xmt_dv_s1_end_xfer => d1_xmt_dv_s1_end_xfer,
      reset_n => xmt_clk_reset_n
    );


  --the_clock_2, which is an e_ptf_instance
  the_clock_2 : clock_2
    port map(
      master_address => clock_2_out_address,
      master_nativeaddress => clock_2_out_nativeaddress,
      master_read => clock_2_out_read,
      master_write => clock_2_out_write,
      master_writedata => clock_2_out_writedata,
      slave_endofpacket => clock_2_in_endofpacket,
      slave_readdata => clock_2_in_readdata,
      slave_waitrequest => clock_2_in_waitrequest,
      master_clk => xmt_clk,
      master_endofpacket => clock_2_out_endofpacket,
      master_readdata => clock_2_out_readdata,
      master_reset_n => clock_2_out_reset_n,
      master_waitrequest => clock_2_out_waitrequest,
      slave_address => clock_2_in_address,
      slave_clk => clk,
      slave_nativeaddress => clock_2_in_nativeaddress,
      slave_read => clock_2_in_read,
      slave_reset_n => clock_2_in_reset_n,
      slave_write => clock_2_in_write,
      slave_writedata => clock_2_in_writedata
    );


  --the_clock_3_in, which is an e_instance
  the_clock_3_in : clock_3_in_arbitrator
    port map(
      clock_3_in_address => clock_3_in_address,
      clock_3_in_endofpacket_from_sa => clock_3_in_endofpacket_from_sa,
      clock_3_in_nativeaddress => clock_3_in_nativeaddress,
      clock_3_in_read => clock_3_in_read,
      clock_3_in_readdata_from_sa => clock_3_in_readdata_from_sa,
      clock_3_in_reset_n => clock_3_in_reset_n,
      clock_3_in_waitrequest_from_sa => clock_3_in_waitrequest_from_sa,
      clock_3_in_write => clock_3_in_write,
      clock_3_in_writedata => clock_3_in_writedata,
      cpu_0_data_master_granted_clock_3_in => cpu_0_data_master_granted_clock_3_in,
      cpu_0_data_master_qualified_request_clock_3_in => cpu_0_data_master_qualified_request_clock_3_in,
      cpu_0_data_master_read_data_valid_clock_3_in => cpu_0_data_master_read_data_valid_clock_3_in,
      cpu_0_data_master_requests_clock_3_in => cpu_0_data_master_requests_clock_3_in,
      d1_clock_3_in_end_xfer => d1_clock_3_in_end_xfer,
      clk => clk,
      clock_3_in_endofpacket => clock_3_in_endofpacket,
      clock_3_in_readdata => clock_3_in_readdata,
      clock_3_in_waitrequest => clock_3_in_waitrequest,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      reset_n => clk_reset_n
    );


  --the_clock_3_out, which is an e_instance
  the_clock_3_out : clock_3_out_arbitrator
    port map(
      clock_3_out_address_to_slave => clock_3_out_address_to_slave,
      clock_3_out_readdata => clock_3_out_readdata,
      clock_3_out_reset_n => clock_3_out_reset_n,
      clock_3_out_waitrequest => clock_3_out_waitrequest,
      clk => xmt_clk,
      clock_3_out_address => clock_3_out_address,
      clock_3_out_granted_xmt_data_s1 => clock_3_out_granted_xmt_data_s1,
      clock_3_out_qualified_request_xmt_data_s1 => clock_3_out_qualified_request_xmt_data_s1,
      clock_3_out_read => clock_3_out_read,
      clock_3_out_read_data_valid_xmt_data_s1 => clock_3_out_read_data_valid_xmt_data_s1,
      clock_3_out_requests_xmt_data_s1 => clock_3_out_requests_xmt_data_s1,
      clock_3_out_write => clock_3_out_write,
      clock_3_out_writedata => clock_3_out_writedata,
      d1_xmt_data_s1_end_xfer => d1_xmt_data_s1_end_xfer,
      reset_n => xmt_clk_reset_n
    );


  --the_clock_3, which is an e_ptf_instance
  the_clock_3 : clock_3
    port map(
      master_address => clock_3_out_address,
      master_nativeaddress => clock_3_out_nativeaddress,
      master_read => clock_3_out_read,
      master_write => clock_3_out_write,
      master_writedata => clock_3_out_writedata,
      slave_endofpacket => clock_3_in_endofpacket,
      slave_readdata => clock_3_in_readdata,
      slave_waitrequest => clock_3_in_waitrequest,
      master_clk => xmt_clk,
      master_endofpacket => clock_3_out_endofpacket,
      master_readdata => clock_3_out_readdata,
      master_reset_n => clock_3_out_reset_n,
      master_waitrequest => clock_3_out_waitrequest,
      slave_address => clock_3_in_address,
      slave_clk => clk,
      slave_nativeaddress => clock_3_in_nativeaddress,
      slave_read => clock_3_in_read,
      slave_reset_n => clock_3_in_reset_n,
      slave_write => clock_3_in_write,
      slave_writedata => clock_3_in_writedata
    );


  --the_cpu_0_jtag_debug_module, which is an e_instance
  the_cpu_0_jtag_debug_module : cpu_0_jtag_debug_module_arbitrator
    port map(
      cpu_0_data_master_granted_cpu_0_jtag_debug_module => cpu_0_data_master_granted_cpu_0_jtag_debug_module,
      cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
      cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
      cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_requests_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_requests_cpu_0_jtag_debug_module => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
      cpu_0_jtag_debug_module_address => cpu_0_jtag_debug_module_address,
      cpu_0_jtag_debug_module_begintransfer => cpu_0_jtag_debug_module_begintransfer,
      cpu_0_jtag_debug_module_byteenable => cpu_0_jtag_debug_module_byteenable,
      cpu_0_jtag_debug_module_chipselect => cpu_0_jtag_debug_module_chipselect,
      cpu_0_jtag_debug_module_debugaccess => cpu_0_jtag_debug_module_debugaccess,
      cpu_0_jtag_debug_module_readdata_from_sa => cpu_0_jtag_debug_module_readdata_from_sa,
      cpu_0_jtag_debug_module_reset => cpu_0_jtag_debug_module_reset,
      cpu_0_jtag_debug_module_resetrequest_from_sa => cpu_0_jtag_debug_module_resetrequest_from_sa,
      cpu_0_jtag_debug_module_write => cpu_0_jtag_debug_module_write,
      cpu_0_jtag_debug_module_writedata => cpu_0_jtag_debug_module_writedata,
      d1_cpu_0_jtag_debug_module_end_xfer => d1_cpu_0_jtag_debug_module_end_xfer,
      clk => clk,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_debugaccess => cpu_0_data_master_debugaccess,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      cpu_0_instruction_master_address_to_slave => cpu_0_instruction_master_address_to_slave,
      cpu_0_instruction_master_latency_counter => cpu_0_instruction_master_latency_counter,
      cpu_0_instruction_master_read => cpu_0_instruction_master_read,
      cpu_0_jtag_debug_module_readdata => cpu_0_jtag_debug_module_readdata,
      cpu_0_jtag_debug_module_resetrequest => cpu_0_jtag_debug_module_resetrequest,
      reset_n => clk_reset_n
    );


  --the_cpu_0_custom_instruction_master, which is an e_instance
  the_cpu_0_custom_instruction_master : cpu_0_custom_instruction_master_arbitrator
    port map(
      cpu_0_custom_instruction_master_combo_result => cpu_0_custom_instruction_master_combo_result,
      cpu_0_custom_instruction_master_reset_n => cpu_0_custom_instruction_master_reset_n,
      endian_cpu_0_s1_select => endian_cpu_0_s1_select,
      clk => clk,
      endian_cpu_0_s1_result_from_sa => endian_cpu_0_s1_result_from_sa,
      reset_n => clk_reset_n
    );


  --the_cpu_0_data_master, which is an e_instance
  the_cpu_0_data_master : cpu_0_data_master_arbitrator
    port map(
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_irq => cpu_0_data_master_irq,
      cpu_0_data_master_readdata => cpu_0_data_master_readdata,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      clk => clk,
      clock_0_in_readdata_from_sa => clock_0_in_readdata_from_sa,
      clock_0_in_waitrequest_from_sa => clock_0_in_waitrequest_from_sa,
      clock_1_in_readdata_from_sa => clock_1_in_readdata_from_sa,
      clock_1_in_waitrequest_from_sa => clock_1_in_waitrequest_from_sa,
      clock_2_in_readdata_from_sa => clock_2_in_readdata_from_sa,
      clock_2_in_waitrequest_from_sa => clock_2_in_waitrequest_from_sa,
      clock_3_in_readdata_from_sa => clock_3_in_readdata_from_sa,
      clock_3_in_waitrequest_from_sa => clock_3_in_waitrequest_from_sa,
      cpu_0_data_master_address => cpu_0_data_master_address,
      cpu_0_data_master_debugaccess => cpu_0_data_master_debugaccess,
      cpu_0_data_master_granted_clock_0_in => cpu_0_data_master_granted_clock_0_in,
      cpu_0_data_master_granted_clock_1_in => cpu_0_data_master_granted_clock_1_in,
      cpu_0_data_master_granted_clock_2_in => cpu_0_data_master_granted_clock_2_in,
      cpu_0_data_master_granted_clock_3_in => cpu_0_data_master_granted_clock_3_in,
      cpu_0_data_master_granted_cpu_0_jtag_debug_module => cpu_0_data_master_granted_cpu_0_jtag_debug_module,
      cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 => cpu_0_data_master_granted_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_granted_lcd_16207_0_control_slave => cpu_0_data_master_granted_lcd_16207_0_control_slave,
      cpu_0_data_master_granted_onchip_memory_0_s1 => cpu_0_data_master_granted_onchip_memory_0_s1,
      cpu_0_data_master_qualified_request_clock_0_in => cpu_0_data_master_qualified_request_clock_0_in,
      cpu_0_data_master_qualified_request_clock_1_in => cpu_0_data_master_qualified_request_clock_1_in,
      cpu_0_data_master_qualified_request_clock_2_in => cpu_0_data_master_qualified_request_clock_2_in,
      cpu_0_data_master_qualified_request_clock_3_in => cpu_0_data_master_qualified_request_clock_3_in,
      cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
      cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 => cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_qualified_request_lcd_16207_0_control_slave => cpu_0_data_master_qualified_request_lcd_16207_0_control_slave,
      cpu_0_data_master_qualified_request_onchip_memory_0_s1 => cpu_0_data_master_qualified_request_onchip_memory_0_s1,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_read_data_valid_clock_0_in => cpu_0_data_master_read_data_valid_clock_0_in,
      cpu_0_data_master_read_data_valid_clock_1_in => cpu_0_data_master_read_data_valid_clock_1_in,
      cpu_0_data_master_read_data_valid_clock_2_in => cpu_0_data_master_read_data_valid_clock_2_in,
      cpu_0_data_master_read_data_valid_clock_3_in => cpu_0_data_master_read_data_valid_clock_3_in,
      cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
      cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 => cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave => cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave,
      cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
      cpu_0_data_master_requests_clock_0_in => cpu_0_data_master_requests_clock_0_in,
      cpu_0_data_master_requests_clock_1_in => cpu_0_data_master_requests_clock_1_in,
      cpu_0_data_master_requests_clock_2_in => cpu_0_data_master_requests_clock_2_in,
      cpu_0_data_master_requests_clock_3_in => cpu_0_data_master_requests_clock_3_in,
      cpu_0_data_master_requests_cpu_0_jtag_debug_module => cpu_0_data_master_requests_cpu_0_jtag_debug_module,
      cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 => cpu_0_data_master_requests_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_requests_lcd_16207_0_control_slave => cpu_0_data_master_requests_lcd_16207_0_control_slave,
      cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_requests_onchip_memory_0_s1,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_jtag_debug_module_readdata_from_sa => cpu_0_jtag_debug_module_readdata_from_sa,
      d1_clock_0_in_end_xfer => d1_clock_0_in_end_xfer,
      d1_clock_1_in_end_xfer => d1_clock_1_in_end_xfer,
      d1_clock_2_in_end_xfer => d1_clock_2_in_end_xfer,
      d1_clock_3_in_end_xfer => d1_clock_3_in_end_xfer,
      d1_cpu_0_jtag_debug_module_end_xfer => d1_cpu_0_jtag_debug_module_end_xfer,
      d1_dm9000a_0_avalon_slave_0_end_xfer => d1_dm9000a_0_avalon_slave_0_end_xfer,
      d1_jtag_uart_0_avalon_jtag_slave_end_xfer => d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
      d1_lcd_16207_0_control_slave_end_xfer => d1_lcd_16207_0_control_slave_end_xfer,
      d1_onchip_memory_0_s1_end_xfer => d1_onchip_memory_0_s1_end_xfer,
      dm9000a_0_avalon_slave_0_irq_from_sa => dm9000a_0_avalon_slave_0_irq_from_sa,
      dm9000a_0_avalon_slave_0_readdata_from_sa => dm9000a_0_avalon_slave_0_readdata_from_sa,
      jtag_uart_0_avalon_jtag_slave_irq_from_sa => jtag_uart_0_avalon_jtag_slave_irq_from_sa,
      jtag_uart_0_avalon_jtag_slave_readdata_from_sa => jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
      jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa => jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
      lcd_16207_0_control_slave_readdata_from_sa => lcd_16207_0_control_slave_readdata_from_sa,
      lcd_16207_0_control_slave_wait_counter_eq_0 => lcd_16207_0_control_slave_wait_counter_eq_0,
      lcd_16207_0_control_slave_wait_counter_eq_1 => lcd_16207_0_control_slave_wait_counter_eq_1,
      onchip_memory_0_s1_readdata_from_sa => onchip_memory_0_s1_readdata_from_sa,
      registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
      reset_n => clk_reset_n
    );


  --the_cpu_0_instruction_master, which is an e_instance
  the_cpu_0_instruction_master : cpu_0_instruction_master_arbitrator
    port map(
      cpu_0_instruction_master_address_to_slave => cpu_0_instruction_master_address_to_slave,
      cpu_0_instruction_master_latency_counter => cpu_0_instruction_master_latency_counter,
      cpu_0_instruction_master_readdata => cpu_0_instruction_master_readdata,
      cpu_0_instruction_master_readdatavalid => cpu_0_instruction_master_readdatavalid,
      cpu_0_instruction_master_waitrequest => cpu_0_instruction_master_waitrequest,
      clk => clk,
      cpu_0_instruction_master_address => cpu_0_instruction_master_address,
      cpu_0_instruction_master_granted_cpu_0_jtag_debug_module => cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_granted_onchip_memory_0_s1 => cpu_0_instruction_master_granted_onchip_memory_0_s1,
      cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module => cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 => cpu_0_instruction_master_qualified_request_onchip_memory_0_s1,
      cpu_0_instruction_master_read => cpu_0_instruction_master_read,
      cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module => cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 => cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1,
      cpu_0_instruction_master_requests_cpu_0_jtag_debug_module => cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
      cpu_0_instruction_master_requests_onchip_memory_0_s1 => cpu_0_instruction_master_requests_onchip_memory_0_s1,
      cpu_0_jtag_debug_module_readdata_from_sa => cpu_0_jtag_debug_module_readdata_from_sa,
      d1_cpu_0_jtag_debug_module_end_xfer => d1_cpu_0_jtag_debug_module_end_xfer,
      d1_onchip_memory_0_s1_end_xfer => d1_onchip_memory_0_s1_end_xfer,
      onchip_memory_0_s1_readdata_from_sa => onchip_memory_0_s1_readdata_from_sa,
      reset_n => clk_reset_n
    );


  --the_cpu_0, which is an e_ptf_instance
  the_cpu_0 : cpu_0
    port map(
      E_ci_combo_a => cpu_0_custom_instruction_master_combo_a,
      E_ci_combo_b => cpu_0_custom_instruction_master_combo_b,
      E_ci_combo_c => cpu_0_custom_instruction_master_combo_c,
      E_ci_combo_dataa => cpu_0_custom_instruction_master_combo_dataa,
      E_ci_combo_datab => cpu_0_custom_instruction_master_combo_datab,
      E_ci_combo_estatus => cpu_0_custom_instruction_master_combo_estatus,
      E_ci_combo_ipending => cpu_0_custom_instruction_master_combo_ipending,
      E_ci_combo_n => cpu_0_custom_instruction_master_combo_n,
      E_ci_combo_readra => cpu_0_custom_instruction_master_combo_readra,
      E_ci_combo_readrb => cpu_0_custom_instruction_master_combo_readrb,
      E_ci_combo_status => cpu_0_custom_instruction_master_combo_status,
      E_ci_combo_writerc => cpu_0_custom_instruction_master_combo_writerc,
      d_address => cpu_0_data_master_address,
      d_byteenable => cpu_0_data_master_byteenable,
      d_read => cpu_0_data_master_read,
      d_write => cpu_0_data_master_write,
      d_writedata => cpu_0_data_master_writedata,
      i_address => cpu_0_instruction_master_address,
      i_read => cpu_0_instruction_master_read,
      jtag_debug_module_debugaccess_to_roms => cpu_0_data_master_debugaccess,
      jtag_debug_module_readdata => cpu_0_jtag_debug_module_readdata,
      jtag_debug_module_resetrequest => cpu_0_jtag_debug_module_resetrequest,
      E_ci_combo_result => cpu_0_custom_instruction_master_combo_result,
      clk => clk,
      d_irq => cpu_0_data_master_irq,
      d_readdata => cpu_0_data_master_readdata,
      d_waitrequest => cpu_0_data_master_waitrequest,
      i_readdata => cpu_0_instruction_master_readdata,
      i_readdatavalid => cpu_0_instruction_master_readdatavalid,
      i_waitrequest => cpu_0_instruction_master_waitrequest,
      jtag_debug_module_address => cpu_0_jtag_debug_module_address,
      jtag_debug_module_begintransfer => cpu_0_jtag_debug_module_begintransfer,
      jtag_debug_module_byteenable => cpu_0_jtag_debug_module_byteenable,
      jtag_debug_module_clk => clk,
      jtag_debug_module_debugaccess => cpu_0_jtag_debug_module_debugaccess,
      jtag_debug_module_reset => cpu_0_jtag_debug_module_reset,
      jtag_debug_module_select => cpu_0_jtag_debug_module_chipselect,
      jtag_debug_module_write => cpu_0_jtag_debug_module_write,
      jtag_debug_module_writedata => cpu_0_jtag_debug_module_writedata,
      reset_n => cpu_0_custom_instruction_master_reset_n
    );


  --the_dm9000a_0_avalon_slave_0, which is an e_instance
  the_dm9000a_0_avalon_slave_0 : dm9000a_0_avalon_slave_0_arbitrator
    port map(
      cpu_0_data_master_granted_dm9000a_0_avalon_slave_0 => cpu_0_data_master_granted_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0 => cpu_0_data_master_qualified_request_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0 => cpu_0_data_master_read_data_valid_dm9000a_0_avalon_slave_0,
      cpu_0_data_master_requests_dm9000a_0_avalon_slave_0 => cpu_0_data_master_requests_dm9000a_0_avalon_slave_0,
      d1_dm9000a_0_avalon_slave_0_end_xfer => d1_dm9000a_0_avalon_slave_0_end_xfer,
      dm9000a_0_avalon_slave_0_address => dm9000a_0_avalon_slave_0_address,
      dm9000a_0_avalon_slave_0_chipselect_n => dm9000a_0_avalon_slave_0_chipselect_n,
      dm9000a_0_avalon_slave_0_irq_from_sa => dm9000a_0_avalon_slave_0_irq_from_sa,
      dm9000a_0_avalon_slave_0_read_n => dm9000a_0_avalon_slave_0_read_n,
      dm9000a_0_avalon_slave_0_readdata_from_sa => dm9000a_0_avalon_slave_0_readdata_from_sa,
      dm9000a_0_avalon_slave_0_reset_n => dm9000a_0_avalon_slave_0_reset_n,
      dm9000a_0_avalon_slave_0_write_n => dm9000a_0_avalon_slave_0_write_n,
      dm9000a_0_avalon_slave_0_writedata => dm9000a_0_avalon_slave_0_writedata,
      clk => clk,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      dm9000a_0_avalon_slave_0_irq => dm9000a_0_avalon_slave_0_irq,
      dm9000a_0_avalon_slave_0_readdata => dm9000a_0_avalon_slave_0_readdata,
      reset_n => clk_reset_n
    );


  --the_dm9000a_0, which is an e_ptf_instance
  the_dm9000a_0 : dm9000a_0
    port map(
      ENET_CLK => internal_ENET_CLK_from_the_dm9000a_0,
      ENET_CMD => internal_ENET_CMD_from_the_dm9000a_0,
      ENET_CS_N => internal_ENET_CS_N_from_the_dm9000a_0,
      ENET_DATA => ENET_DATA_to_and_from_the_dm9000a_0,
      ENET_RD_N => internal_ENET_RD_N_from_the_dm9000a_0,
      ENET_RST_N => internal_ENET_RST_N_from_the_dm9000a_0,
      ENET_WR_N => internal_ENET_WR_N_from_the_dm9000a_0,
      oDATA => dm9000a_0_avalon_slave_0_readdata,
      oINT => dm9000a_0_avalon_slave_0_irq,
      ENET_INT => ENET_INT_to_the_dm9000a_0,
      iCLK => clk,
      iCMD => dm9000a_0_avalon_slave_0_address,
      iCS_N => dm9000a_0_avalon_slave_0_chipselect_n,
      iDATA => dm9000a_0_avalon_slave_0_writedata,
      iOSC_50 => iOSC_50_to_the_dm9000a_0,
      iRD_N => dm9000a_0_avalon_slave_0_read_n,
      iRST_N => dm9000a_0_avalon_slave_0_reset_n,
      iWR_N => dm9000a_0_avalon_slave_0_write_n
    );


  --the_endian_cpu_0_s1, which is an e_instance
  the_endian_cpu_0_s1 : endian_cpu_0_s1_arbitrator
    port map(
      endian_cpu_0_s1_dataa => endian_cpu_0_s1_dataa,
      endian_cpu_0_s1_datab => endian_cpu_0_s1_datab,
      endian_cpu_0_s1_result_from_sa => endian_cpu_0_s1_result_from_sa,
      clk => clk,
      cpu_0_custom_instruction_master_combo_dataa => cpu_0_custom_instruction_master_combo_dataa,
      cpu_0_custom_instruction_master_combo_datab => cpu_0_custom_instruction_master_combo_datab,
      endian_cpu_0_s1_result => endian_cpu_0_s1_result,
      endian_cpu_0_s1_select => endian_cpu_0_s1_select,
      reset_n => clk_reset_n
    );


  --the_endian_cpu_0, which is an e_ptf_instance
  the_endian_cpu_0 : endian_cpu_0
    port map(
      result => endian_cpu_0_s1_result,
      dataa => endian_cpu_0_s1_dataa,
      datab => endian_cpu_0_s1_datab
    );


  --the_jtag_uart_0_avalon_jtag_slave, which is an e_instance
  the_jtag_uart_0_avalon_jtag_slave : jtag_uart_0_avalon_jtag_slave_arbitrator
    port map(
      cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
      cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave => cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
      d1_jtag_uart_0_avalon_jtag_slave_end_xfer => d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
      jtag_uart_0_avalon_jtag_slave_address => jtag_uart_0_avalon_jtag_slave_address,
      jtag_uart_0_avalon_jtag_slave_chipselect => jtag_uart_0_avalon_jtag_slave_chipselect,
      jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa => jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa,
      jtag_uart_0_avalon_jtag_slave_irq_from_sa => jtag_uart_0_avalon_jtag_slave_irq_from_sa,
      jtag_uart_0_avalon_jtag_slave_read_n => jtag_uart_0_avalon_jtag_slave_read_n,
      jtag_uart_0_avalon_jtag_slave_readdata_from_sa => jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
      jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa => jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa,
      jtag_uart_0_avalon_jtag_slave_reset_n => jtag_uart_0_avalon_jtag_slave_reset_n,
      jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa => jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
      jtag_uart_0_avalon_jtag_slave_write_n => jtag_uart_0_avalon_jtag_slave_write_n,
      jtag_uart_0_avalon_jtag_slave_writedata => jtag_uart_0_avalon_jtag_slave_writedata,
      clk => clk,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      jtag_uart_0_avalon_jtag_slave_dataavailable => jtag_uart_0_avalon_jtag_slave_dataavailable,
      jtag_uart_0_avalon_jtag_slave_irq => jtag_uart_0_avalon_jtag_slave_irq,
      jtag_uart_0_avalon_jtag_slave_readdata => jtag_uart_0_avalon_jtag_slave_readdata,
      jtag_uart_0_avalon_jtag_slave_readyfordata => jtag_uart_0_avalon_jtag_slave_readyfordata,
      jtag_uart_0_avalon_jtag_slave_waitrequest => jtag_uart_0_avalon_jtag_slave_waitrequest,
      reset_n => clk_reset_n
    );


  --the_jtag_uart_0, which is an e_ptf_instance
  the_jtag_uart_0 : jtag_uart_0
    port map(
      av_irq => jtag_uart_0_avalon_jtag_slave_irq,
      av_readdata => jtag_uart_0_avalon_jtag_slave_readdata,
      av_waitrequest => jtag_uart_0_avalon_jtag_slave_waitrequest,
      dataavailable => jtag_uart_0_avalon_jtag_slave_dataavailable,
      readyfordata => jtag_uart_0_avalon_jtag_slave_readyfordata,
      av_address => jtag_uart_0_avalon_jtag_slave_address,
      av_chipselect => jtag_uart_0_avalon_jtag_slave_chipselect,
      av_read_n => jtag_uart_0_avalon_jtag_slave_read_n,
      av_write_n => jtag_uart_0_avalon_jtag_slave_write_n,
      av_writedata => jtag_uart_0_avalon_jtag_slave_writedata,
      clk => clk,
      rst_n => jtag_uart_0_avalon_jtag_slave_reset_n
    );


  --the_lcd_16207_0_control_slave, which is an e_instance
  the_lcd_16207_0_control_slave : lcd_16207_0_control_slave_arbitrator
    port map(
      cpu_0_data_master_granted_lcd_16207_0_control_slave => cpu_0_data_master_granted_lcd_16207_0_control_slave,
      cpu_0_data_master_qualified_request_lcd_16207_0_control_slave => cpu_0_data_master_qualified_request_lcd_16207_0_control_slave,
      cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave => cpu_0_data_master_read_data_valid_lcd_16207_0_control_slave,
      cpu_0_data_master_requests_lcd_16207_0_control_slave => cpu_0_data_master_requests_lcd_16207_0_control_slave,
      d1_lcd_16207_0_control_slave_end_xfer => d1_lcd_16207_0_control_slave_end_xfer,
      lcd_16207_0_control_slave_address => lcd_16207_0_control_slave_address,
      lcd_16207_0_control_slave_begintransfer => lcd_16207_0_control_slave_begintransfer,
      lcd_16207_0_control_slave_read => lcd_16207_0_control_slave_read,
      lcd_16207_0_control_slave_readdata_from_sa => lcd_16207_0_control_slave_readdata_from_sa,
      lcd_16207_0_control_slave_wait_counter_eq_0 => lcd_16207_0_control_slave_wait_counter_eq_0,
      lcd_16207_0_control_slave_wait_counter_eq_1 => lcd_16207_0_control_slave_wait_counter_eq_1,
      lcd_16207_0_control_slave_write => lcd_16207_0_control_slave_write,
      lcd_16207_0_control_slave_writedata => lcd_16207_0_control_slave_writedata,
      clk => clk,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      lcd_16207_0_control_slave_readdata => lcd_16207_0_control_slave_readdata,
      reset_n => clk_reset_n
    );


  --the_lcd_16207_0, which is an e_ptf_instance
  the_lcd_16207_0 : lcd_16207_0
    port map(
      LCD_E => internal_LCD_E_from_the_lcd_16207_0,
      LCD_RS => internal_LCD_RS_from_the_lcd_16207_0,
      LCD_RW => internal_LCD_RW_from_the_lcd_16207_0,
      LCD_data => LCD_data_to_and_from_the_lcd_16207_0,
      irq => lcd_16207_0_control_slave_irq,
      readdata => lcd_16207_0_control_slave_readdata,
      address => lcd_16207_0_control_slave_address,
      begintransfer => lcd_16207_0_control_slave_begintransfer,
      read => lcd_16207_0_control_slave_read,
      write => lcd_16207_0_control_slave_write,
      writedata => lcd_16207_0_control_slave_writedata
    );


  --the_onchip_memory_0_s1, which is an e_instance
  the_onchip_memory_0_s1 : onchip_memory_0_s1_arbitrator
    port map(
      cpu_0_data_master_granted_onchip_memory_0_s1 => cpu_0_data_master_granted_onchip_memory_0_s1,
      cpu_0_data_master_qualified_request_onchip_memory_0_s1 => cpu_0_data_master_qualified_request_onchip_memory_0_s1,
      cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
      cpu_0_data_master_requests_onchip_memory_0_s1 => cpu_0_data_master_requests_onchip_memory_0_s1,
      cpu_0_instruction_master_granted_onchip_memory_0_s1 => cpu_0_instruction_master_granted_onchip_memory_0_s1,
      cpu_0_instruction_master_qualified_request_onchip_memory_0_s1 => cpu_0_instruction_master_qualified_request_onchip_memory_0_s1,
      cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1 => cpu_0_instruction_master_read_data_valid_onchip_memory_0_s1,
      cpu_0_instruction_master_requests_onchip_memory_0_s1 => cpu_0_instruction_master_requests_onchip_memory_0_s1,
      d1_onchip_memory_0_s1_end_xfer => d1_onchip_memory_0_s1_end_xfer,
      onchip_memory_0_s1_address => onchip_memory_0_s1_address,
      onchip_memory_0_s1_byteenable => onchip_memory_0_s1_byteenable,
      onchip_memory_0_s1_chipselect => onchip_memory_0_s1_chipselect,
      onchip_memory_0_s1_clken => onchip_memory_0_s1_clken,
      onchip_memory_0_s1_readdata_from_sa => onchip_memory_0_s1_readdata_from_sa,
      onchip_memory_0_s1_write => onchip_memory_0_s1_write,
      onchip_memory_0_s1_writedata => onchip_memory_0_s1_writedata,
      registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1 => registered_cpu_0_data_master_read_data_valid_onchip_memory_0_s1,
      clk => clk,
      cpu_0_data_master_address_to_slave => cpu_0_data_master_address_to_slave,
      cpu_0_data_master_byteenable => cpu_0_data_master_byteenable,
      cpu_0_data_master_read => cpu_0_data_master_read,
      cpu_0_data_master_waitrequest => cpu_0_data_master_waitrequest,
      cpu_0_data_master_write => cpu_0_data_master_write,
      cpu_0_data_master_writedata => cpu_0_data_master_writedata,
      cpu_0_instruction_master_address_to_slave => cpu_0_instruction_master_address_to_slave,
      cpu_0_instruction_master_latency_counter => cpu_0_instruction_master_latency_counter,
      cpu_0_instruction_master_read => cpu_0_instruction_master_read,
      onchip_memory_0_s1_readdata => onchip_memory_0_s1_readdata,
      reset_n => clk_reset_n
    );


  --the_onchip_memory_0, which is an e_ptf_instance
  the_onchip_memory_0 : onchip_memory_0
    port map(
      readdata => onchip_memory_0_s1_readdata,
      address => onchip_memory_0_s1_address,
      byteenable => onchip_memory_0_s1_byteenable,
      chipselect => onchip_memory_0_s1_chipselect,
      clk => clk,
      clken => onchip_memory_0_s1_clken,
      write => onchip_memory_0_s1_write,
      writedata => onchip_memory_0_s1_writedata
    );


  --the_rcv_data_s1, which is an e_instance
  the_rcv_data_s1 : rcv_data_s1_arbitrator
    port map(
      clock_1_out_granted_rcv_data_s1 => clock_1_out_granted_rcv_data_s1,
      clock_1_out_qualified_request_rcv_data_s1 => clock_1_out_qualified_request_rcv_data_s1,
      clock_1_out_read_data_valid_rcv_data_s1 => clock_1_out_read_data_valid_rcv_data_s1,
      clock_1_out_requests_rcv_data_s1 => clock_1_out_requests_rcv_data_s1,
      d1_rcv_data_s1_end_xfer => d1_rcv_data_s1_end_xfer,
      rcv_data_s1_address => rcv_data_s1_address,
      rcv_data_s1_chipselect => rcv_data_s1_chipselect,
      rcv_data_s1_readdata_from_sa => rcv_data_s1_readdata_from_sa,
      rcv_data_s1_reset_n => rcv_data_s1_reset_n,
      rcv_data_s1_write_n => rcv_data_s1_write_n,
      rcv_data_s1_writedata => rcv_data_s1_writedata,
      clk => rcv_clk,
      clock_1_out_address_to_slave => clock_1_out_address_to_slave,
      clock_1_out_nativeaddress => clock_1_out_nativeaddress,
      clock_1_out_read => clock_1_out_read,
      clock_1_out_write => clock_1_out_write,
      clock_1_out_writedata => clock_1_out_writedata,
      rcv_data_s1_readdata => rcv_data_s1_readdata,
      reset_n => rcv_clk_reset_n
    );


  --the_rcv_data, which is an e_ptf_instance
  the_rcv_data : rcv_data
    port map(
      readdata => rcv_data_s1_readdata,
      address => rcv_data_s1_address,
      chipselect => rcv_data_s1_chipselect,
      clk => rcv_clk,
      in_port => in_port_to_the_rcv_data,
      reset_n => rcv_data_s1_reset_n,
      write_n => rcv_data_s1_write_n,
      writedata => rcv_data_s1_writedata
    );


  --the_rcv_dv_s1, which is an e_instance
  the_rcv_dv_s1 : rcv_dv_s1_arbitrator
    port map(
      clock_0_out_granted_rcv_dv_s1 => clock_0_out_granted_rcv_dv_s1,
      clock_0_out_qualified_request_rcv_dv_s1 => clock_0_out_qualified_request_rcv_dv_s1,
      clock_0_out_read_data_valid_rcv_dv_s1 => clock_0_out_read_data_valid_rcv_dv_s1,
      clock_0_out_requests_rcv_dv_s1 => clock_0_out_requests_rcv_dv_s1,
      d1_rcv_dv_s1_end_xfer => d1_rcv_dv_s1_end_xfer,
      rcv_dv_s1_address => rcv_dv_s1_address,
      rcv_dv_s1_chipselect => rcv_dv_s1_chipselect,
      rcv_dv_s1_readdata_from_sa => rcv_dv_s1_readdata_from_sa,
      rcv_dv_s1_reset_n => rcv_dv_s1_reset_n,
      rcv_dv_s1_write_n => rcv_dv_s1_write_n,
      rcv_dv_s1_writedata => rcv_dv_s1_writedata,
      clk => rcv_clk,
      clock_0_out_address_to_slave => clock_0_out_address_to_slave,
      clock_0_out_nativeaddress => clock_0_out_nativeaddress,
      clock_0_out_read => clock_0_out_read,
      clock_0_out_write => clock_0_out_write,
      clock_0_out_writedata => clock_0_out_writedata,
      rcv_dv_s1_readdata => rcv_dv_s1_readdata,
      reset_n => rcv_clk_reset_n
    );


  --the_rcv_dv, which is an e_ptf_instance
  the_rcv_dv : rcv_dv
    port map(
      readdata => rcv_dv_s1_readdata,
      address => rcv_dv_s1_address,
      chipselect => rcv_dv_s1_chipselect,
      clk => rcv_clk,
      in_port => in_port_to_the_rcv_dv,
      reset_n => rcv_dv_s1_reset_n,
      write_n => rcv_dv_s1_write_n,
      writedata => rcv_dv_s1_writedata
    );


  --the_xmt_data_s1, which is an e_instance
  the_xmt_data_s1 : xmt_data_s1_arbitrator
    port map(
      clock_3_out_granted_xmt_data_s1 => clock_3_out_granted_xmt_data_s1,
      clock_3_out_qualified_request_xmt_data_s1 => clock_3_out_qualified_request_xmt_data_s1,
      clock_3_out_read_data_valid_xmt_data_s1 => clock_3_out_read_data_valid_xmt_data_s1,
      clock_3_out_requests_xmt_data_s1 => clock_3_out_requests_xmt_data_s1,
      d1_xmt_data_s1_end_xfer => d1_xmt_data_s1_end_xfer,
      xmt_data_s1_address => xmt_data_s1_address,
      xmt_data_s1_chipselect => xmt_data_s1_chipselect,
      xmt_data_s1_reset_n => xmt_data_s1_reset_n,
      xmt_data_s1_write_n => xmt_data_s1_write_n,
      xmt_data_s1_writedata => xmt_data_s1_writedata,
      clk => xmt_clk,
      clock_3_out_address_to_slave => clock_3_out_address_to_slave,
      clock_3_out_nativeaddress => clock_3_out_nativeaddress,
      clock_3_out_read => clock_3_out_read,
      clock_3_out_write => clock_3_out_write,
      clock_3_out_writedata => clock_3_out_writedata,
      reset_n => xmt_clk_reset_n
    );


  --the_xmt_data, which is an e_ptf_instance
  the_xmt_data : xmt_data
    port map(
      out_port => internal_out_port_from_the_xmt_data,
      address => xmt_data_s1_address,
      chipselect => xmt_data_s1_chipselect,
      clk => xmt_clk,
      reset_n => xmt_data_s1_reset_n,
      write_n => xmt_data_s1_write_n,
      writedata => xmt_data_s1_writedata
    );


  --the_xmt_dv_s1, which is an e_instance
  the_xmt_dv_s1 : xmt_dv_s1_arbitrator
    port map(
      clock_2_out_granted_xmt_dv_s1 => clock_2_out_granted_xmt_dv_s1,
      clock_2_out_qualified_request_xmt_dv_s1 => clock_2_out_qualified_request_xmt_dv_s1,
      clock_2_out_read_data_valid_xmt_dv_s1 => clock_2_out_read_data_valid_xmt_dv_s1,
      clock_2_out_requests_xmt_dv_s1 => clock_2_out_requests_xmt_dv_s1,
      d1_xmt_dv_s1_end_xfer => d1_xmt_dv_s1_end_xfer,
      xmt_dv_s1_address => xmt_dv_s1_address,
      xmt_dv_s1_chipselect => xmt_dv_s1_chipselect,
      xmt_dv_s1_reset_n => xmt_dv_s1_reset_n,
      xmt_dv_s1_write_n => xmt_dv_s1_write_n,
      xmt_dv_s1_writedata => xmt_dv_s1_writedata,
      clk => xmt_clk,
      clock_2_out_address_to_slave => clock_2_out_address_to_slave,
      clock_2_out_nativeaddress => clock_2_out_nativeaddress,
      clock_2_out_read => clock_2_out_read,
      clock_2_out_write => clock_2_out_write,
      clock_2_out_writedata => clock_2_out_writedata,
      reset_n => xmt_clk_reset_n
    );


  --the_xmt_dv, which is an e_ptf_instance
  the_xmt_dv : xmt_dv
    port map(
      out_port => internal_out_port_from_the_xmt_dv,
      address => xmt_dv_s1_address,
      chipselect => xmt_dv_s1_chipselect,
      clk => xmt_clk,
      reset_n => xmt_dv_s1_reset_n,
      write_n => xmt_dv_s1_write_n,
      writedata => xmt_dv_s1_writedata
    );


  --reset is asserted asynchronously and deasserted synchronously
  nios_system_reset_clk_domain_synch : nios_system_reset_clk_domain_synch_module
    port map(
      data_out => clk_reset_n,
      clk => clk,
      data_in => module_input,
      reset_n => reset_n_sources
    );

  module_input <= std_logic'('1');

  --reset sources mux, which is an e_mux
  reset_n_sources <= Vector_To_Std_Logic(NOT (((((((std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(NOT reset_n))) OR std_logic_vector'("00000000000000000000000000000000")) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_jtag_debug_module_resetrequest_from_sa)))) OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(cpu_0_jtag_debug_module_resetrequest_from_sa)))) OR std_logic_vector'("00000000000000000000000000000000")) OR std_logic_vector'("00000000000000000000000000000000"))));
  --reset is asserted asynchronously and deasserted synchronously
  nios_system_reset_rcv_clk_domain_synch : nios_system_reset_rcv_clk_domain_synch_module
    port map(
      data_out => rcv_clk_reset_n,
      clk => rcv_clk,
      data_in => module_input1,
      reset_n => reset_n_sources
    );

  module_input1 <= std_logic'('1');

  --reset is asserted asynchronously and deasserted synchronously
  nios_system_reset_xmt_clk_domain_synch : nios_system_reset_xmt_clk_domain_synch_module
    port map(
      data_out => xmt_clk_reset_n,
      clk => xmt_clk,
      data_in => module_input2,
      reset_n => reset_n_sources
    );

  module_input2 <= std_logic'('1');

  --clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_0_out_endofpacket <= std_logic'('0');
  --clock_1_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_1_out_endofpacket <= std_logic'('0');
  --clock_2_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_2_out_endofpacket <= std_logic'('0');
  --clock_3_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
  clock_3_out_endofpacket <= std_logic'('0');
  --vhdl renameroo for output signals
  ENET_CLK_from_the_dm9000a_0 <= internal_ENET_CLK_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  ENET_CMD_from_the_dm9000a_0 <= internal_ENET_CMD_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  ENET_CS_N_from_the_dm9000a_0 <= internal_ENET_CS_N_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  ENET_RD_N_from_the_dm9000a_0 <= internal_ENET_RD_N_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  ENET_RST_N_from_the_dm9000a_0 <= internal_ENET_RST_N_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  ENET_WR_N_from_the_dm9000a_0 <= internal_ENET_WR_N_from_the_dm9000a_0;
  --vhdl renameroo for output signals
  LCD_E_from_the_lcd_16207_0 <= internal_LCD_E_from_the_lcd_16207_0;
  --vhdl renameroo for output signals
  LCD_RS_from_the_lcd_16207_0 <= internal_LCD_RS_from_the_lcd_16207_0;
  --vhdl renameroo for output signals
  LCD_RW_from_the_lcd_16207_0 <= internal_LCD_RW_from_the_lcd_16207_0;
  --vhdl renameroo for output signals
  out_port_from_the_xmt_data <= internal_out_port_from_the_xmt_data;
  --vhdl renameroo for output signals
  out_port_from_the_xmt_dv <= internal_out_port_from_the_xmt_dv;

end europa;


--synthesis translate_off

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your libraries here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>

entity test_bench is 
end entity test_bench;


architecture europa of test_bench is
component nios_system is 
           port (
                 -- 1) global signals:
                    signal clk : IN STD_LOGIC;
                    signal rcv_clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal xmt_clk : IN STD_LOGIC;

                 -- the_dm9000a_0
                    signal ENET_CLK_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal ENET_CMD_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal ENET_CS_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal ENET_DATA_to_and_from_the_dm9000a_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal ENET_INT_to_the_dm9000a_0 : IN STD_LOGIC;
                    signal ENET_RD_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal ENET_RST_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal ENET_WR_N_from_the_dm9000a_0 : OUT STD_LOGIC;
                    signal iOSC_50_to_the_dm9000a_0 : IN STD_LOGIC;

                 -- the_lcd_16207_0
                    signal LCD_E_from_the_lcd_16207_0 : OUT STD_LOGIC;
                    signal LCD_RS_from_the_lcd_16207_0 : OUT STD_LOGIC;
                    signal LCD_RW_from_the_lcd_16207_0 : OUT STD_LOGIC;
                    signal LCD_data_to_and_from_the_lcd_16207_0 : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- the_rcv_data
                    signal in_port_to_the_rcv_data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- the_rcv_dv
                    signal in_port_to_the_rcv_dv : IN STD_LOGIC;

                 -- the_xmt_data
                    signal out_port_from_the_xmt_data : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

                 -- the_xmt_dv
                    signal out_port_from_the_xmt_dv : OUT STD_LOGIC
                 );
end component nios_system;

                signal ENET_CLK_from_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_CMD_from_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_CS_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_DATA_to_and_from_the_dm9000a_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal ENET_INT_to_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_RD_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_RST_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal ENET_WR_N_from_the_dm9000a_0 :  STD_LOGIC;
                signal LCD_E_from_the_lcd_16207_0 :  STD_LOGIC;
                signal LCD_RS_from_the_lcd_16207_0 :  STD_LOGIC;
                signal LCD_RW_from_the_lcd_16207_0 :  STD_LOGIC;
                signal LCD_data_to_and_from_the_lcd_16207_0 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal clk :  STD_LOGIC;
                signal clock_0_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_0_out_endofpacket :  STD_LOGIC;
                signal clock_1_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_1_out_endofpacket :  STD_LOGIC;
                signal clock_2_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_2_out_endofpacket :  STD_LOGIC;
                signal clock_3_in_endofpacket_from_sa :  STD_LOGIC;
                signal clock_3_out_endofpacket :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_a :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_b :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_c :  STD_LOGIC_VECTOR (4 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_estatus :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_ipending :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_n :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal cpu_0_custom_instruction_master_combo_readra :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_readrb :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_status :  STD_LOGIC;
                signal cpu_0_custom_instruction_master_combo_writerc :  STD_LOGIC;
                signal iOSC_50_to_the_dm9000a_0 :  STD_LOGIC;
                signal in_port_to_the_rcv_data :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal in_port_to_the_rcv_dv :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa :  STD_LOGIC;
                signal jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa :  STD_LOGIC;
                signal lcd_16207_0_control_slave_irq :  STD_LOGIC;
                signal out_port_from_the_xmt_data :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal out_port_from_the_xmt_dv :  STD_LOGIC;
                signal rcv_clk :  STD_LOGIC;
                signal reset_n :  STD_LOGIC;
                signal xmt_clk :  STD_LOGIC;


-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your component and signal declaration here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>


begin

  --Set us up the Dut
  DUT : nios_system
    port map(
      ENET_CLK_from_the_dm9000a_0 => ENET_CLK_from_the_dm9000a_0,
      ENET_CMD_from_the_dm9000a_0 => ENET_CMD_from_the_dm9000a_0,
      ENET_CS_N_from_the_dm9000a_0 => ENET_CS_N_from_the_dm9000a_0,
      ENET_DATA_to_and_from_the_dm9000a_0 => ENET_DATA_to_and_from_the_dm9000a_0,
      ENET_RD_N_from_the_dm9000a_0 => ENET_RD_N_from_the_dm9000a_0,
      ENET_RST_N_from_the_dm9000a_0 => ENET_RST_N_from_the_dm9000a_0,
      ENET_WR_N_from_the_dm9000a_0 => ENET_WR_N_from_the_dm9000a_0,
      LCD_E_from_the_lcd_16207_0 => LCD_E_from_the_lcd_16207_0,
      LCD_RS_from_the_lcd_16207_0 => LCD_RS_from_the_lcd_16207_0,
      LCD_RW_from_the_lcd_16207_0 => LCD_RW_from_the_lcd_16207_0,
      LCD_data_to_and_from_the_lcd_16207_0 => LCD_data_to_and_from_the_lcd_16207_0,
      out_port_from_the_xmt_data => out_port_from_the_xmt_data,
      out_port_from_the_xmt_dv => out_port_from_the_xmt_dv,
      ENET_INT_to_the_dm9000a_0 => ENET_INT_to_the_dm9000a_0,
      clk => clk,
      iOSC_50_to_the_dm9000a_0 => iOSC_50_to_the_dm9000a_0,
      in_port_to_the_rcv_data => in_port_to_the_rcv_data,
      in_port_to_the_rcv_dv => in_port_to_the_rcv_dv,
      rcv_clk => rcv_clk,
      reset_n => reset_n,
      xmt_clk => xmt_clk
    );


  process
  begin
    clk <= '0';
    loop
       wait for 10 ns;
       clk <= not clk;
    end loop;
  end process;
  process
  begin
    rcv_clk <= '0';
    loop
       wait for 20 ns;
       rcv_clk <= not rcv_clk;
    end loop;
  end process;
  PROCESS
    BEGIN
       reset_n <= '0';
       wait for 200 ns;
       reset_n <= '1'; 
    WAIT;
  END PROCESS;
  process
  begin
    xmt_clk <= '0';
    loop
       wait for 20 ns;
       xmt_clk <= not xmt_clk;
    end loop;
  end process;


-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add additional architecture here
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>


end europa;



--synthesis translate_on
